Capacitor structures, decoupling structures and semiconductor devices including the same

Patent metadata

Field	Value
Publication number	US-10692968-B2
Application number	US-201916697484-A
Country	US
Kind code	B2
Filing date	Nov 27, 2019
Priority date	Sep 5, 2014
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a decoupling structure comprising a first capacitor and a second capacitor, the decoupling structure comprising:
first conductive patterns that each extend in a vertical direction;
a first conductive plate commonly connected to the first conductive patterns;
second conductive patterns that each extend in the vertical direction;
a second conductive plate commonly connected to the second conductive patterns;
a common electrode between ones of the first conductive patterns and between ones of the second conductive patterns;
a first supporting layer supporting the first conductive patterns and the second conductive patterns and spaced apart from the first and second conductive plates; and
a second supporting layer supporting the first conductive patterns and the second conductive patterns and above the first supporting layer,
wherein the first conductive patterns and the second conductive patterns are spaced apart from each other with a separation region therebetween,
wherein the first supporting layer comprises first openings, and the second supporting layer comprises second openings respectively overlapped with the first openings,
wherein a top surface of the second supporting layer is at a level higher than a top surface of at least one of the first and second conductive patterns, and
wherein the second supporting layer is thicker than the first supporting layer.

2. The integrated circuit device of claim 1 , wherein the common electrode comprises horizontal portions on a top surface and a bottom surface of the first supporting layer and the top surface and a bottom surface of the second supporting layer and vertical connecting portions in the first and second openings.

3. The integrated circuit device of claim 1 , wherein the common electrode comprises:
a first region below the first supporting layer; and
a second region between the first supporting layer and the second supporting layer,
wherein the first and second regions are in the separation region.

4. The integrated circuit device of claim 3 , wherein at least one of the first and second regions comprises a void.

5. The integrated circuit device of claim 1 , wherein the first and second openings are not in the separation region.

6. The integrated circuit device of claim 1 , further comprising an insulation layer filling a space between the first conductive plate and second conductive plate.

7. The integrated circuit device of claim 1 , further comprising an insulation layer extended horizontally on the first conductive plate and the second conductive plate to cover lower sidewalls of the first and second conductive patterns and filling a space between the first conductive plate and second conductive plate,
wherein the insulation layer comprises a horizontally extended portion and a vertically extended portion in the separation region.

8. The integrated circuit device of claim 1 , further comprising an insulation layer in the separation region.

9. The integrated circuit device of claim 8 , further comprising a substrate underneath the decoupling structure,
wherein the insulation layer comprises an upper portion and a lower portion that protrudes toward the substrate between the first conductive plate and the second conductive plate.

10. The integrated circuit device of claim 9 , further comprising:
a lower insulating layer below the first conductive patterns and the second conductive patterns.

11. The integrated circuit device of claim 10 , wherein the lower portion of the insulation layer protrudes within the lower insulating layer.

12. The integrated circuit device of claim 10 , wherein a bottom surface of the insulation layer in the separation region is lower than bottom surfaces of the first and second conductive plates.

13. The integrated circuit device of claim 1 , wherein the first conductive patterns are spaced apart from each other along a first horizontal direction at a first interval,
wherein the second conductive patterns are spaced apart from each other along the first horizontal direction at a second interval, and
wherein the second conductive patterns are spaced apart from the first conductive patterns in the first horizontal direction with the separation region therebetween, and the separation region has a width in the first horizontal direction greater than the first interval or the second interval.

14. An integrated circuit device comprising:
a decoupling structure comprising a first capacitor and a second capacitor, the decoupling structure comprising:
a first plurality of conductive patterns that each extend in a vertical direction;
a first conductive plate commonly connected to the first plurality of conductive patterns;
a second plurality of conductive patterns that each extend in the vertical direction;
a second conductive plate commonly connected to the second plurality of conductive patterns;
a common electrode between ones of the first plurality of conductive patterns and between ones of the second plurality of conductive patterns;
a first supporting layer supporting the first plurality of conductive patterns and the second plurality of conductive patterns and spaced apart from the first and second conductive plates; and
a second supporting layer supporting the first plurality of conductive patterns and the second plurality of conductive patterns and above the first supporting layer,
wherein the first plurality of conductive patterns and the second plurality of conductive patterns are spaced apart from each other with a separation region therebetween,
wherein the common electrode comprises a first region below the first supporting layer and a second region between the first supporting layer and the second supporting layer, and the first and second regions are in the separation region,
wherein a top surface of the second supporting layer is at a level higher than a top surface of at least one of the first plurality of conductive patterns and the second plurality of conductive patterns, and
wherein the second supporting layer is thicker than the first supporting layer.

15. The integrated circuit device of claim 14 , wherein at least one of the first and second regions comprises a void.

16. The integrated circuit device of claim 15 , wherein the first supporting layer comprises first openings and the second supporting layer comprises second openings, and
wherein the first and second openings are not in the separation region.

17. The integrated circuit device of claim 14 , further comprising:
a lower insulating layer below the first plurality of conductive patterns and the second plurality of conductive patterns.

18. An integrated circuit device comprising:
a decoupling structure comprising a first capacitor and a second capacitor, the decoupling structure comprising:
first conductive patterns that each extend in a vertical direction;
a first conductive plate commonly connected to the first conductive patterns;
second conductive patterns that each extend in the vertical direction;
a second conductive plate commonly connected to the second conductive patterns;
a common electrode between ones of the first conductive patterns and between ones of the second conductive patterns;
a first supporting layer supporting the first conductive patterns and the second conductive patterns and spaced apart from the first and second conductive plates;
a second supporting layer supporting the first conductive patterns and the second conductive patterns and above the first suppo

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jong-Min
• Jun Jongryul
• Kim Eun A
• Lim Jung-Bum

Classifications

• H10D84/212 Primary

  of only capacitors · CPC title

• H10D1/714

  having horizontal extensions · CPC title

• H10D1/711

  having non-planar surfaces, e.g. formed by texturisation · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title