High density self-routing metal-oxide-metal capacitor

Patent metadata

Field	Value
Publication number	US-10692967-B1
Application number	US-201816209768-A
Country	US
Kind code	B1
Filing date	Dec 4, 2018
Priority date	Dec 4, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A self-routing capacitor for an integrated circuit having: a first electrode comprising a first base region and a first finger, the first finger extending from a wall of the first base region in a first direction; a second electrode comprising a second base region and a second finger; the second finger extending from a wall of the second base region in a second direction substantially parallel to and opposing the first direction, the second finger coupled to the first finger; a third electrode comprising a third base region and a third finger, the third finger extending from a first wall of the third base in the second direction; and a fourth electrode comprising a fourth finger, the fourth finger extending from a second wall of the third base region in the first direction. The capacitor being coupled to other metal layers through a base region of an electrode.

First claim

What is claimed is:

1. A self-routing capacitor for an integrated circuit, the self-routing capacitor comprising:
a first structure comprising:
a first electrode having a first base region and a first set of two or more fingers;
a second electrode having a second base region and a second set of two or more fingers, the second set of two or more fingers interdigitated with the first set of two or more fingers;
a third electrode having a third base region and a third set of two or more fingers, a finger of the first set of two or more fingers being coupled to a finger of the third set of two or more fingers; and
a fourth set of two or more fingers that are coupled to a first wall of the second base region and interdigitated with the third set of two or more fingers.

2. The self-routing capacitor of claim 1 , wherein the first set of two or more fingers are formed in a first metal layer and the finger of the first set of two or more fingers is coupled to the finger of the third set of two or more fingers through a second metal layer and the first and third base regions.

3. The self-routing capacitor of claim 1 , wherein the self-routing capacitor is coupled to other layers of the integrated circuit through one or more of the first base region, the second base region, or the third base region.

4. The self-routing capacitor of claim 1 , wherein the first set of two or more fingers are formed in a first metal layer and at least one finger in the first set of two or more fingers has a dimension that is substantially equal to a minimum size for a finger without a via in the first metal layer.

5. The self-routing capacitor of claim 1 , wherein the self-routing capacitor further comprises:
a second structure that comprises an instance of the first structure, wherein the second electrode of the first structure is coupled to an electrode of the second structure.

6. The self-routing capacitor of claim 5 , wherein the second electrode of the first structure is formed in a first metal layer and the second electrode of the first structure is coupled to the electrode of the second structure in the first metal layer.

7. The self-routing capacitor of claim 1 , wherein the first electrode, the second electrode, the third electrode, and the fourth set of two or more fingers are formed in a first metal layer of the integrated circuit.

8. The self-routing capacitor of claim 1 , wherein:
the second set of two or more fingers are formed on a second wall of the second base region; and
the second wall of the second base region opposes the first wall of the second base region.

9. The self-routing capacitor of claim 8 , wherein each finger in the second set of two or more fingers is formed at substantially opposite ends of the first wall of the second base region.

10. A method for forming a self-routing capacitor in a metal layer of an integrated circuit, the method comprising:
forming a base capacitor structure having a bottom plate and a top plate, wherein:
the bottom plate has a first base region and a first set of two or more fingers;

the top plate has a second base region and a second set of two or more fingers, the second set of two or more fingers interdigitated with the first set of two or more fingers; and
forming first unit capacitor structure comprising the base capacitor structure and a mirrored capacitor structure, wherein:
the mirrored capacitor structure is a mirrored instance of the base capacitor structure,
the second base region is coupled to a corresponding base region of a top plate of the mirrored capacitor structure that corresponds to the top plate of the base capacitor structure, and
a finger of the first set of two or more fingers is coupled to a corresponding finger of a bottom plate of the mirrored capacitor structure.

11. The method of claim 10 , wherein forming the base capacitor structure comprises forming a finger of the first set of two or more fingers or a finger of the second set of two or more fingers to have a minimum width allowed for an uncontacted finger in the metal layer.

12. The method of claim 10 , wherein forming the base capacitor structure comprises forming interdigitated fingers of both the bottom plate of the base capacitor structure and the top plate of the base capacitor structure to have a minimum pitch allowed for uncontacted electrodes in the metal layer.

13. The method of claim 10 , further comprising:
coupling the finger of the first set of two or more fingers to the corresponding finger of the bottom plate of the mirrored capacitor structure through the first base region and a corresponding base region of a bottom plate of the mirrored capacitor structure.

14. The method of claim 10 , wherein coupling the second base region to the corresponding base region of the top plate of the mirrored capacitor structure comprises at least partially overlapping the second base region and the corresponding base region of the top plate of the mirrored capacitor structure.

15. The method of claim 10 , wherein coupling the second base region to the corresponding base region of the top plate of the mirrored capacitor structure comprises:
disposing the mirrored capacitor structure adjacent to the base capacitor structure to cause the second base region to abut the corresponding base region of the top plate of the mirrored capacitor structure.

16. The method of claim 10 , further comprising:
expanding a size of the self-routing capacitor by coupling a second unit capacitor structure to the first unit capacitor structure by overlapping the first base region with a corresponding base region of a bottom plate of the second unit capacitor structure.

17. The method of claim 10 , further comprising:
expanding a size of the sell-routing capacitor by coupling a second unit capacitor structure to the first unit capacitor structure by disposing the second unit capacitor structure adjacent to the first unit capacitor structure to cause the first base region to abut a corresponding base region of a bottom plate of the second unit capacitor structure.

18. The method of claim 10 , wherein the mirrored instance of the base capacitor structure is mirrored across an axis that is substantially parallel to a length of the first base region.

19. A capacitor formed in a metal layer of an integrated circuit, the capacitor comprising:
a first electrode comprising a first base region and a first finger that extends from the first base region in a first direction;
a second electrode comprising a second base region and a second finger, the second finger extending from a wall of the second base region in a second direction, the second finger coupled to the first finger;
a third electrode comprising a third base region and a third finger, the third finger extending from a first wall of the third base region in the second direction; and a fourth electrode comprising a fourth base region and a fourth finger, wherein: the fourth finger extends from a second wall of the fourth base region in the first direction;
wherein:
the first electrode at least partially overlaps the third electrode along an axis that is substantially parallel to first direction, and the second electrode overlaps the fourth electrode along the axis, and
the capacitor is only coupled to other metal layers through a base region of an electrode of the capacitor.

20. The capacitor of claim 10 , wherein the first electrode and the second electrode are formed in a first metal layer and the first finger is coupled to the second finger in a second

Assignees

• Analog Devices Inc

Inventors

• Chen Baozhen
• Fernando Lalinda D
• O'Halloran Micah Galletta
• Shaw Andrew Wayne

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/692 Primary

  Electrodes · CPC title

• H10D1/714 Primary

  having horizontal extensions · CPC title

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title