3-dimensional NOR string arrays in segmented stacks

Patent metadata

Field	Value
Publication number	US-10692874-B2
Application number	US-201816006573-A
Country	US
Kind code	B2
Filing date	Jun 12, 2018
Priority date	Jun 20, 2017
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

First claim

We claim:

1. A memory structure, comprising:
a semiconductor substrate having a planar surface, the semiconductor substrate having circuitry formed therein and thereon;
first and second memory modules provided above the planar surface, the second memory module being provided on top of the first memory module, wherein each memory module comprises:
a plurality of stacks of active strips, the stacks being spaced from each other along a first direction substantially parallel the planar surface, each active strip running lengthwise along a second direction that is also substantially parallel the planar surface but orthogonal to the first direction, the active strips within each stack being provided one on top of another along a third direction that is substantially perpendicular to the planar surface, each active strip comprising semiconductor layers that form drain, source and channel regions of thin-film storage transistors organized as NOR strings; and
a set of local word line conductors each running along the third direction to provide as gate electrodes to storage transistors in a designated one of the stacks of active strips; and

a first set of global word line conductors provided between the first memory module and the second memory module, wherein the global word line conductors in the first set of global word line conductors are (i) spaced from each other along the second direction and each running along the first direction, and (ii) each in direct contact with selected local word line conductors of both the first and second memory modules.

2. The memory structure of claim 1 , further comprising a second set of global word line conductors and a third set of global word line conductors, formed above the second memory module and below the first memory module, respectively, wherein, within each of the second and third sets of global word line conductors, the global word line conductors are spaced from each other along the second direction and each running along the first direction, and wherein the global word line conductors of the second and third set of global conductors are each in direct contact with selected local word line conductors in the second memory module and the first memory module, respectively.

3. The memory structure of claim 1 , wherein the first set of global word line conductors connects the selected local word line conductors to circuitry in the semiconductor substrate.

4. The memory structure of claim 3 , wherein the circuitry in the semiconductor substrate comprises voltage sources.

Assignees

• Sunrise Memory Corp

Inventors

• Harari Eli
• Chien Wu-Yi

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• C25B11/075

  consisting of a single catalytic element or catalytic compound · CPC title

• C30B29/64

  Flat crystals, e.g. plates, strips or discs · CPC title

• C30B29/02

  Elements · CPC title

• C30B7/14

  the crystallising materials being formed by chemical reactions in the solution · CPC title