Tracking and correction of timing signals

Patent metadata

Field	Value
Publication number	US-10692550-B2
Application number	US-201715808508-A
Country	US
Kind code	B2
Filing date	Nov 9, 2017
Priority date	Dec 11, 2014
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the timing signals returned to the interface. A timing delta from the comparison can be applied to calculate a correction value make adjustments that can include adjustment to a subsequent timing signal, adjustment to a reference voltage setting associated with the subsequent timing signal, other adjustments, or combinations thereof. Additional apparatus, systems, and methods are disclosed.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of memory dies; and
a logic die coupled to the plurality of memory dies, the logic die including:
a first interface to transmit a clock signal, a strobe signal, or both a clock signal and a strobe signal to a selected memory die of the plurality of memory dies;
a second interface to receive a delayed version of the clock signal returned to the logic die from the selected memory die, a delayed version of the strobe signal returned to the logic die from the selected memory die, or both a delayed version of the clock signal and a delayed version of the strobe signal returned to the logic die from the selected memory die;
timing compare circuitry to compare the clock signal to the delayed version of the clock signal returned to the logic die from the selected memory die or to compare the strobe signal to the delayed version of the strobe signal returned to the logic die from the selected memory die, the timing compare circuitry to provide a timing delta from the comparison;
a correction module to calculate a correction value to adjust a subsequent clock signal to the selected memory die or to adjust a reference voltage setting associated with a subsequent strobe signal to the selected memory die; and
a controller to apply the correction value to the subsequent clock signal or the reference voltage setting.

2. The apparatus of claim 1 , wherein the plurality of memory dies is arranged in a vertical stack using through-substrate vias.

3. The apparatus of claim 1 , wherein the plurality of memory dies is arranged in a vertical stack.

4. The apparatus of claim 3 , wherein the plurality of memory dies is disposed on the logic die.

5. The apparatus of claim 3 , wherein the plurality of memory dies is disposed separate from the logic die and adjacent to the logic die.

6. The apparatus of claim 1 , wherein the memory dies of the plurality of memory dies are coupled to a timing line and to a return timing line with the timing line separate from the return timing line the timing line being one or more communication paths to transmit the strobe or the clock from the first interface and the return timing line being one or more return communication paths to return the strobe or the clock to the second interface on which the delayed version of the clock signal returns to the logic die or the delayed version of the strobe signal returns to the logic die.

7. The apparatus of claim 1 , wherein the selected memory device is located in the plurality of memory dies such that the clock signal, the strobe signal, or both the clock signal and the strobe signal is transmitted to the selected memory die through another memory device of the plurality of memory dies or the delayed version of the clock signal, the delayed version of the strobe signal, or both a delayed version of the clock signal and a delayed version of the strobe signal is returned to the logic die from the other memory device, the other memory device having a voltage domain independent and different from the selected memory die.

8. An apparatus comprising:
a plurality of memory dies; and
a logic die coupled to the plurality of memory dies, the logic die including:
an interface to transmit a clock signal, a strobe signal, or both a clock signal and a strobe signal to a selected memory die of the plurality of memory dies;
timing compare circuitry to compare the clock signal or the strobe signal to a respective return clock signal or return strobe signal from the selected memory die and to provide a timing delta from the comparison, the return clock signal being a returned signal of the transmitted clock signal and the return strobe signal being a returned signal of the transmitted strobe signal;
a correction module to calculate a correction value to adjust a subsequent clock signal to the selected memory die or to adjust a reference voltage setting associated with a subsequent strobe signal to the selected memory die, the calculation based on voltage shift data derived from the timing delta; and
a controller to apply the correction value to the subsequent clock signal or the reference voltage setting, wherein the correction module includes firmware having routines to validate correction values calculated by the correction module, using stored information, over life of the selected memory die operating in the apparatus.

9. The apparatus of claim 8 , wherein the selected memory device is located in the plurality of memory dies such that the clock signal, the strobe signal, or both the clock signal and the strobe signal is transmitted to the selected memory die through another memory device of the plurality of memory dies or the return clock signal, the return strobe signal or both the return clock signal and the return strobe signal is returned to the logic die from the other memory device, the other memory device having a voltage domain independent and different from the selected memory die.

10. An apparatus comprising:
a plurality of memory dies; and
a logic die coupled to the plurality of memory dies, the logic die including:
an interface to transmit a clock signal, a strobe signal, or both a clock signal and a strobe signal to a selected memory die of the plurality of memory dies;
timing compare circuitry to compare the clock signal or the strobe signal to a respective return clock signal or return strobe signal from the selected memory die and to provide a timing delta from the comparison;
a correction module to calculate a correction value to adjust a subsequent clock signal to the selected memory die or to adjust a reference voltage setting associated with a subsequent strobe signal to the selected memory die, the calculation based on voltage shift data derived from the timing delta; and
a controller to apply the correction value to the subsequent clock signal or the reference voltage setting, wherein the correction module includes firmware having routines to validate correction values calculated b the correction module, using stored information, over life of the selected memory die operating in the apparatus, wherein the correction value is positive when the timing delta indicates that corruption to the transmitted clock signal is in a negative direction.

11. A method comprising:
transmitting a clock signal, a strobe signal, or both a clock signal and a strobe signal to a selected memory die of a plurality of memory dies coupled to a logic die, using a first interface of the logic die;
receiving a delayed version of the clock signal returned to the logic die from the selected memory die, a delayed version of the strobe signal returned to the logic die from the selected memory die, or both a delayed version of the clock signal and a delayed version of the strobe signal returned to the logic die from the selected memory die, using a second interface of the logic die;
comparing the clock signal to the delayed version of the clock signal returned to the logic die from the selected memory die or comparing the strobe signal to the delayed version of the strobe signal returned to the logic die from the selected memory die, using timing compare circuitry of the logic die, and providing a timing delta from the comparison;
calculating a correction value to adjust a subsequent clock signal to the selected memory die or to adjust a reference voltage setting associated with a subsequent strobe signal to the selected memory die, using a correction module of the logic die;
applying the correction value to the subsequent clock signal or the reference voltage setting, using a controller of the logic die.

12. The method of claim 11 , wherein the plurality of memory dies is

Assignees

• Micron Technology Inc

Inventors

• King Gregory A

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title