Memory array structure, in-memory computing apparatus and method thereof

Patent metadata

Field	Value
Publication number	US-10692549-B1
Application number	US-201916572604-A
Country	US
Kind code	B1
Filing date	Sep 17, 2019
Priority date	Sep 17, 2019
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A memory array structure that includes memory columns having first bit lines and second bit lines is introduced. Each of the memory columns includes a bit line pair, a pre-charge switch pair and a first switch pair. Output voltages from the first bit lines and the second bit lines are used to generated a first average voltage and a second average voltage, respectively. One of the first average voltage and the second average voltage is a lower average voltage and another one of the first average voltage and the second average voltage is a higher average voltage. The pre-charge switch pair and the first switch pair of a selected memory column among the plurality of memory columns are controlled to repeatedly perform an incremental step to increment the lower average voltage by a step voltage until the lower average voltage is greater than the higher average voltage.

First claim

What is claimed is:

1. A memory array structure, comprising:
a plurality of memory columns, comprising a plurality of first bit lines and a plurality of second bit lines, wherein each of the plurality of memory columns comprises:
a bit line pair, comprising a first bit line and a second bit line, wherein the first bit line is one of the plurality of first bit lines and the second bit line is one of the plurality of second bit lines;
a pre-charge switch pair, comprising a first pre-charge switch and a second pre-charge switch, wherein the first pre-charge switch is coupled to the first bit line and the second pre-charge switch is coupled to the second bit line; and
a first switch pair, comprising a first switch and a second switch, wherein the first switch is coupled to the first bit line and the second switch is coupled to the second bit line,

wherein output voltages from the plurality of first bit lines are used to generated a first average voltage,
output voltages from the plurality of second bit lines are used to generated a second average voltage,
when the first average voltage is smaller than the second average voltage, the first average voltage is a lower average voltage and the second average voltage is a higher average voltage,
when the first average voltage is not smaller than the second average voltage, the first average voltage is the higher average voltage and the second average voltage is the lower average voltage,
wherein the pre-charge switch pair and the first switch pair of a selected memory column among the plurality of memory columns are controlled to repeatedly perform an incremental step to increment the lower average voltage by a step voltage until the lower average voltage is greater than the higher average voltage.

2. The memory array structure of claim 1 , wherein
the selected memory column is determined according to a comparison result between the first average voltage and the second average voltage.

3. The memory array structure of claim 1 , wherein
the step voltage is determined according to a pre-determined reference voltage, and
the step voltage is independent from the first average voltage and the second average voltage.

4. The memory array structure of claim 1 , wherein
the first pre-charge switch is coupled between the first bit line and a first reference node, and the second pre-charge switch is coupled between the second bit line and the first reference node, and
the first switch is coupled between the first bit line and a second reference node, and the second switch is coupled between the second bit line and the second reference node, wherein the first reference node receives a first reference voltage, the second reference node receives a second reference voltage, and the first reference voltage is greater than the second reference voltage.

5. The memory array structure of claim 4 , wherein each of the plurality of memory columns further comprises:
a second switch pair, comprising a third switch and a fourth switch, wherein the third switch is coupled to the first bit line and the fourth switch is coupled to the second bit line; and
a capacitor pair, comprising a first capacitor and a second capacitor, wherein the first capacitor of the capacitor pair is coupled between the third switch of the second switch pair and a connection node between the first pre-charge switch of the pre-charge switch pair and the first switch of the first switch pair, and the second capacitor of the capacitor pair is coupled between the fourth switch of the second switch pair and a connection node between the second pre-charge switch of the pre-charge switch pair and the second switch of the first switch pair.

6. The memory array structure of claim 5 , wherein
before the incremental step, the pre-charge pair of each of the plurality of memory columns are turned off and the first switch pair of each of the plurality of memory columns are turned on, and
during the incremental step, a switch among the first switch and the second switch of the selected memory column being associated with the lower average voltage is turned off, and a pre-charge switch among the first pre-charge switch and the second pre-charge switch of the selected memory column being associated with the lower average voltage is turned on.

7. The memory array structure of claim 1 , wherein
the pre-charge switch pair and the first switch pair of the selected memory column among the plurality of memory columns are further controlled to repeatedly perform a decremental step to decrement the higher average voltage until the lower average voltage is greater than the higher average voltage, and
the incremental step to increment the lower average voltage and the decremental step to decrement the higher average voltage are performed simultaneously.

8. An in-memory computing apparatus, comprising:
a memory structure, comprising a plurality of memory columns with a plurality of first bit lines and a plurality of second bit lines; and
a comparator, configured to compare the first average voltage and the second average voltage to determine a lower average voltage and a higher average voltage among the first average voltage and the second average voltage, when the first average voltage is smaller than the second average voltage, the first average voltage is the lower average voltage and the second average voltage is the higher average voltage, and when the first average voltage is not smaller than the second average voltage, the first average voltage is the higher average voltage and the second average voltage is the lower average voltage,
wherein each of the plurality of memory columns comprises:
a bit line pair, comprising a first bit line and a second bit line, wherein the first bit line is one of the plurality of first bit lines and the second bit line is one of the plurality of second bit lines;
a pre-charge switch pair, comprising a first pre-charge switch and a second pre-charge switch, wherein the first pre-charge switch is coupled to the first bit line and the second pre-charge switch is coupled to the second bit line; and
a first switch pair, comprising a first switch and a second switch, wherein the first switch is coupled to the first bit line and the second switch is coupled to the second bit line,

wherein output voltages from the plurality of first bit lines are used to generated a first average voltage, output voltages from the plurality of second bit lines are used to generated a second average voltage,
wherein the pre-charge switch pair and the first switch pair of a selected memory column among the plurality of memory columns are controlled to repeatedly perform an incremental step to increment the lower average voltage by a step voltage until the lower average voltage is greater than the higher average voltage.

9. The in-memory computing apparatus of claim 8 , wherein
the selected memory column is determined according to a comparison result between the first average voltage and the second average voltage.

10. The in-memory computing apparatus of claim 8 ,
the step voltage is determined according to a pre-determined reference voltage, and
the step voltage is independent from the first average voltage and the second average voltage.

11. The in-memory computing apparatus of claim 8 , wherein each of the plurality of memory columns further comprises:
a second switch pair, comprising a third switch and a fourth switch, wherein the third switch is coupled to the first bit line and the fourth switch is coupled to the second bit line; and
a capacitor pair, comprising a first capacitor and a second capacitor, wherein
the first capacitor of the capacitor pair is coupled between the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Yung-Chow
• Chang Chin-Ho
• Horng Jaw-Juinn

Classifications

• H03M1/56

  Input signal compared with linear ramp · CPC title

• G11C11/24

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C7/16 Primary

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title