Display panel and display device

Patent metadata

Field	Value
Publication number	US-10692438-B2
Application number	US-201815892221-A
Country	US
Kind code	B2
Filing date	Feb 8, 2018
Priority date	Oct 30, 2017
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Provided are a display panel and a display device, where a display area of the display panel includes a first display area and a second display area, each of the first display area and the second display area includes a plurality of pixels arranged in an array, and the quantity of pixels in at least one row of pixels in the first display area is less than the quantity of pixels in any row of pixels in the second display area. The display panel further includes a gate driving circuit and a plurality of scan signal lines, and at least one of the scan signal lines provides a scan signal for a row of the pixels. The display panel further includes resistance compensation units connected to the scan signal lines of the first display area, and the resistance compensation units are metal or metal oxide conducting wires.

First claim

What is claimed is:

1. A display panel, comprising: a display area and a non-display area adjacent to the display area,
wherein the display area comprises a first display area and a second display area, each of the first display area and the second display area comprises a plurality of pixels arranged in an array;
wherein a quantity of pixels in at least one row of pixels in the first display area is less than a quantity of pixels in any row of pixels in the second display area;
wherein the display panel further comprises a gate driving circuit and a plurality of scan signal lines, wherein the gate driving circuit is arranged in the non-display area, the plurality of scan signal lines each is connected to an output terminal of the gate driving circuit, and wherein at least one of the plurality of scan signal lines provides a scan signal for a row of the pixels in either the first display area or the second display area;
wherein the display panel further comprises resistance compensation units connected to the scan signal lines of the first display area, wherein the resistance compensation units are formed of metal or metal oxide conducting wires, and wherein the metal or metal oxide conducting wires are in a shape of a fold line, a curve or a spiral;
wherein the display panel further comprises signal lines for providing reference signals to the display panel, wherein a longitudinal extension direction of each of the signal lines is the same as that of each of the plurality of scan signal lines;
wherein one of the signal lines is arranged overlaying one of the resistance compensation units, and has a same pattern as said resistance compensation unit right below it;
wherein an overlaying area between one of the signal lines and a resistance compensation unit right below it forms a capacitor;
wherein the display panel further comprises thin film transistors located in the display area and arranged in one to one correspondence to the pixels;
wherein each of the thin film transistors comprises a gate, a source and a drain, wherein the source and the drain being arranged at a same layer, and the gate and the source being arranged at different layers;
wherein the resistance compensation units are arranged at a same layer and made of a same material as the gate; or
each of the resistance compensation units is arranged at a metal layer between a gate layer and a source layer; or
the resistance compensation units are arranged at a same layer and made of a same material as the source.

2. The display panel according to claim 1 , wherein a resistivity of the resistance compensation units is 0.55-5.6 Ωm.

3. The display panel according to claim 1 , wherein a line width of each of the metal or metal oxide conducting wires is 2.5-3 μm.

4. The display panel according to claim 1 , wherein the resistance compensation units and the scan signal lines are connected through via holes.

5. The display panel according to claim 1 , wherein the resistance compensation units are arranged between the gate driving circuit and the scan signal lines; or
the resistance compensation units are located at ends, far away from the gate driving circuit, of the scan signal lines.

6. The display panel according to claim 5 , wherein each of the pixels comprises: an anode, a light emitting layer and a cathode that are arranged in a stack; and
wherein the resistance compensation units are arranged at a same layer and made of a same material as the anode.

7. The display panel according to claim 1 , wherein an edge of the first display area has a curved line, rounded corner, chamfered corner or notch.

8. The display panel according to claim 7 , wherein the pixel rows in the first display area are respectively connected to various types of scan signal lines; and
wherein at least two of the scan signal lines are respectively connected to one of the resistance compensation units.

9. The display panel according to claim 8 , wherein quantities of pixels in respective pixel rows in the first display area sequentially increase in a column direction; and
wherein resistances of the resistance compensation units connected to a same type of the scan signal lines corresponding to the pixel rows sequentially decrease in the column direction.

10. The display panel according to claim 9 , wherein a difference between a resistance of one of the resistance compensation units corresponding to a pixel row having a smallest quantity of pixels and a resistance of one of the resistance compensation units corresponding to a pixel row having a largest quantity of pixels is not more than 1110Ω.

11. The display panel according to claim 1 , wherein the first display area comprises a first subregion, a middle region and a second subregion, wherein the first subregion and the second subregion are located on both sides of the middle region; and
wherein a part of pixels in each row of pixels in the first display area is located in the first subregion, and remaining pixels in each row of pixels in the first display area are located in the second subregion.

12. The display panel according to claim 11 , wherein the middle region is a hollow region or a transparent display region.

13. The display panel according to claim 12 , wherein the first display area and the second display area are controlled separately or in a coordinated way.

14. A display device, comprising a display panel comprising a display area and a non-display area adjacent to the display area, wherein:
the display area comprises a first display area and a second display area, each of the first display area and the second display area comprises a plurality of pixels arranged in an array; and a quantity of pixels in at least one row of pixels in the first display area is less than a quantity of pixels in any row of pixels in the second display area;
wherein the display panel further comprises a gate driving circuit and a plurality of scan signal lines, wherein the gate driving circuit is arranged in the non-display area, the plurality of scan signal lines each is connected to an output terminal of the gate driving circuit, and at least one of the plurality of scan signal lines provides a scan signal for a row of the pixels in the display area;
wherein the display panel further comprises resistance compensation units connected to the scan signal lines of the first display area;
wherein the resistance compensation units are formed of metal or metal oxide conducting wires, wherein the metal or metal oxide conducting wires are in a shape of a fold line, a curve or a spiral;
wherein the display panel further comprises signal lines for providing reference signals to the display panel, wherein a longitudinal extension direction of each of the signal lines is same as that of each of the plurality of scan signal lines, wherein one of the signal lines is arranged overlaying one of the resistance compensation units, and has a same pattern as said resistance compensation unit right below it,
wherein an overlaying area between one of the signal lines and a resistance compensation unit right below it forms a capacitor;
wherein the display panel further comprises thin film transistors located in the display area and arranged in one to one correspondence to the pixels;
wherein each of the thin film transistors comprising a gate, a source and a drain, wherein the source and the drain being arranged at a same layer, and the gate and the source being arranged at different layers; wherein
the resistance compensation units are arranged at a same layer and made of a same material as the gate; or
each of the resistance compensation units is arranged a

Assignees

• Wuhan Tianma Micro Electronics Co Ltd

Inventors

• Yang Xingxing

Classifications

• H10K59/1315

  comprising structures specially adapted for lowering the resistance · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10K59/00

  Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00 · CPC title