Method of operating virtual address generator and method of operating system including the same

Patent metadata

Field	Value
Publication number	US-10692171-B2
Application number	US-201615353226-A
Country	US
Kind code	B2
Filing date	Nov 16, 2016
Priority date	Nov 17, 2015
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A method of generating a virtual address in a data processing system controller includes receiving and analyzing attribute information which indicates whether user intervention is possible for allocating a memory buffer for storing image data; enabling one of a first virtual address generator or a second virtual address generator based on an analysis result; and generating the virtual address of a data transaction using the enabled virtual address generator.

First claim

What is claimed is:

1. A method of generating a virtual address in a data processing system controller, the method comprising:
receiving attribute information which indicates whether there will be user intervention to allocate a memory buffer for storing image data;
enabling one of a first virtual address generator using a linear mode mapping and a second virtual address generator using a tile mode mapping based on the attribute information; and
generating the virtual address of a data transaction using the enabled virtual address generator;
wherein the first virtual address generator is enabled when the attribute information indicates that there will be user intervention and
the second virtual address generator is enabled when the attribute information indicates that there will not be user intervention.

2. The method of claim 1 , wherein
the first virtual address generator generates the virtual address based on coordinates of a pixel, a size of the pixel, and a size of the image data; and
the second virtual address generator generates the virtual address based on a size of a tile in the image data, a number of the tile to be processed, a size of the data transaction, and a line number in the tile to be processed.

3. The method of claim 2 , wherein the number of the tile to be processed is determined based on a function of a position of the tile and a total number of tiles included in a row of the image data.

4. The method of claim 2 , further comprising
analyzing a pattern of the image data wherein an analysis result indicates whether the image data is rotated image data or unrotated image data and generating information about a processing mode of the image data based on the analysis result,
wherein the one of the first and second virtual address generators is enabled based on the analysis result and the information about the processing mode.

5. The method of claim 4 , wherein
the first virtual address generator is enabled when the processing mode is a raster scan mode for unrotated image data and
the second virtual address generator is enabled when the processing mode is a non-raster scan mode for rotated image data.

6. The method of claim 2 , wherein
the second virtual address generator generates the virtual address to generate a hierarchical tile address map,
the hierarchical tile address map comprises a plurality of super tiles arranged in linear order,
each of the super tiles comprises a plurality of tiles arranged in linear order, and
each of the tiles comprises a plurality of pixels addressed in linear order.

7. A system for generating memory addresses, comprising:
a virtual address generator that includes a first virtual address generator using a linear mode mapping and a second virtual address generator using a tile mode mapping,
wherein the virtual address generator
receives attribute information which indicates whether there will be user intervention to allocate a memory buffer for storing image data,
enables one of the first and second virtual address generators based on the attribute information, and
generates a virtual address of a data transaction using the enabled virtual address generator; and

a memory management unit that translates the virtual address into a physical address, wherein
the first virtual address generator is enabled when the attribute information indicates that there will be user intervention and
the second virtual address generator is enabled when the attribute information indicates that there will not be user intervention.

8. The system of claim 7 , wherein
the first virtual address generator generates the virtual address based on coordinates of a pixel, a size of the pixel, and a size of the image data; and
the second virtual address generator generates the virtual address based on a size of a tile in the image data, a number of the tile to be processed, a size of the data transaction, and a line number in the tile.

9. The system of claim 8 , wherein the number of the tile to be processed is determined based on a function which comprises a position of the tile and a total number of tiles comprised in a row of the image data.

10. The system of claim 8 , further comprising
an image signal processor core that analyzes a pattern of the image data wherein an analysis result indicates whether the image data is rotated image data or unrotated image data and generates information about a mode of processing the image data based on the analysis result,
wherein the one of the first and second virtual address generators is enabled based on the analysis result and the information about the mode of processing.

11. The system of claim 10 , wherein
the first virtual address generator is enabled when the processing mode is a raster scan mode for unrotated image data and
the second virtual address generator is enabled when the processing mode is a non-raster scan mode for rotated image data.

12. The system of claim 8 , further comprising a central processing unit (CPU) that provides a software interface for receiving the attribute information.

13. The system of claim 8 , wherein
the second virtual address generator generates the virtual address to generate a hierarchical tile address map,
the hierarchical tile address map comprises a plurality of super tiles arranged in linear order,
each of the super tiles comprises a plurality of tiles arranged in linear order, and
each of the tiles comprises a plurality of pixels addressed in linear order.

14. A system for generating memory addresses, comprising:
a virtual address generator that includes a first virtual address generator using a linear mode mapping and a second virtual address generator using a tile mode mapping,
wherein the virtual address generator receives attribute information which indicates there will be user intervention to allocate a memory buffer for storing image data, enables one of the first and second virtual address generators based on the attribute information,
wherein the first virtual address generator generates a virtual address based on coordinates of a pixel, a size of the pixel, and a size of the image data; and
the second virtual address generator generates the virtual address based on a size of a tile in the image data, a number of the tile to be processed, a size of data transaction, and a line number in the tile, wherein
the first virtual address generator is enabled when the attribute information indicates that there will be user intervention and
the second virtual address generator is enabled when the attribute information indicates that there will not be user intervention.

15. The system of claim 14 , further comprising
an image signal processor core that analyzes a pattern of the image data wherein an analysis result indicates whether the image data is rotated image data or unrotated image data and generates information about a mode of processing the image data based on the analysis result, wherein
the first virtual address generator is enabled when the processing mode is a raster scan mode and
the second virtual address generator is enabled when the processing mode is a non-raster scan mode for image rotation.

16. The system of claim 14 , further comprising
a memory management unit that translates the virtual address into a physical address; and
a central processing unit (CPU) that provides a software interface for receiving the attribute information.

17. The system of claim 14 , wherein
the number of the tile to be processed is determined based on a function which comprises a position of the tile and a t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Sung Min
• Hur Jae Young
• Jun Min Je

Classifications

• H04N5/76

  Television signal recording · CPC title

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title

• G06T3/606

  by memory addressing or mapping · CPC title