Layouts for connecting contacts with metal tabs or vias

Patent metadata

Field	Value
Publication number	US-10691862-B2
Application number	US-201715644288-A
Country	US
Kind code	B2
Filing date	Jul 7, 2017
Priority date	Jul 7, 2017
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.

First claim

What is claimed:

1. A method implemented in a computer infrastructure comprising:
assigning marker tabs for connecting contacts of semiconductor elements to a metal line to reserve space for future connections between the contacts and the metal line; and
reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements, wherein the connections between the contacts and the metal line comprise a first group of connections comprised of metal tabs on a first level of the metal stack and a second group of connections comprised of vias to connect the contacts to the metal line on a second level of the metal stack which is at a different level than the first level of the metal stack, and the method assigns the first and second groups of connections to alternate the metal tabs and the vias with one another to separate adjacent metal tabs from one another by a via.

2. The method of claim 1 , wherein the contacts are source/drain contacts formed on the semiconductor elements.

3. The method of claim 2 , wherein the source/drain contacts are surrounded by a Shallow Trench Isolation (STI) layer.

4. The method of claim 3 , wherein the connections between the source/drain contacts and the metal line occur after the reassignment of the marker tabs.

5. The method of claim 1 , wherein the metal tabs of the first group of connections formed on the first level of the metal stack are formed by different masking operations.

6. The method of claim 1 , further comprising a third group of connections comprised of local connections within each of the semiconductor elements.

7. The method of claim 1 , further comprising performing at least one additional processing step, after the reassignment to form the first and second groups of connections, to improve yield based on a final layer assignment after reassignment of the marker tabs.

8. The method of claim 7 , wherein the additional processing comprising cutting off corners of the vias to ensure adequate spacing of adjacent ones of the vias.

9. The method of claim 8 , wherein the metal tabs are located between two vias of the vias.

10. The method of claim 8 , wherein the vias are located between two metal tabs of the metal tabs.

11. The method of claim 10 , wherein the semiconductor elements are surrounded by a Shallow Trench Isolation (STI) layer.

12. The method of claim 11 , wherein the contacts are surrounded by the STI layer.

13. A system for connecting source/drain contacts surrounded by an STI layer to a metal line, the system comprising a CPU, a computer readable memory and a computer readable storage device, and configured to:
connect the source/drain contacts to the metal line with marker tabs to reserve space for future connections between the source/drain contacts and the metal line; and
perform across layer reassignment of the marker tabs to assign a first group of the marker tabs to be metal tabs to connect a first group of the source/drain contacts to the metal line at a first level of a metal stack formed over the source/drain contacts and the STI layer, and to assign a second group of the marker tabs to be vias to connect a second group of the source/drain contacts to the metal line at a second layer of the metal stack which is at a different level than the first layer of the metal stack, wherein the system is further configured to assign the first and second groups of marker tabs to alternate the metal tabs and the vias with one another to separate adjacent metal tabs from one another by a via.

14. The system of claim 13 , wherein the metal tabs formed on the first level of the metal stack are formed by different masking operations.

15. The system of claim 13 , wherein the system is further configured to assign a third group of the marker tabs to be connections comprised of local connections within each of the semiconductor elements.

16. The system of claim 13 , further comprising performing at least one additional processing step, after reassignment to form the metal tabs and vias, to improve yield based on a final layer assignment after reassignment of the marker tabs.

17. The system of claim 16 , wherein the additional processing comprising cutting off corners of the vias to ensure adequate spacing of adjacent ones of the vias.

18. A computer program product comprising a computer readable hardware storage device having readable program code embodied in the computer readable hardware storage device, the computer program product including at least one component operable to:
assign marker tabs to connect contacts of semiconductor elements to a metal line to reserve space for future connections between the contacts and the metal line; and
reassign the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements, wherein the contacts are source/drain contacts formed on the semiconductor elements, the connections between the source/drain contacts and the metal line after the reassignment of the marker tabs comprise a first group of connections comprised of metal tabs on a first level of the metal stack and a second group of connections comprised of vias to connect the source/drain contacts to the metal line on a second level of the metal stack which is at a different level than the first level of the metal stack, and the first and second groups of connections are assigned to alternate the metal tabs and the vias with one another to separate adjacent metal tabs from one another by a via.

19. The computer program product of claim 18 , wherein the source/drain contacts are surrounded by a Shallow Trench Isolation (STI) layer.

20. The computer program product of claim 19 , wherein the connections between the source/drain contacts and the metal line after the reassignment of the marker tabs comprise a first group of connections comprised of metal tabs on a first level of the metal stack and a second group of connections comprised of vias to connect the source/drain contacts to the metal line on a second level of the metal stack which is at a different level than the first level of the metal stack.

Assignees

• Globalfoundries Inc

Inventors

• Nayyar Neha
• Dechene Daniel J
• Pritchard David C
• Kluth George J

Classifications

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title