System and methods exchanging data between processors through concurrent shared memory

Patent metadata

Field	Value
Publication number	US-10691612-B2
Application number	US-201816159442-A
Country	US
Kind code	B2
Filing date	Oct 12, 2018
Priority date	Dec 22, 2004
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

First claim

What is claimed:

1. A system comprising:
a central processing unit (CPU);
a graphics processing unit (GPU) coupled with the CPU; and
logic to pass a pointer from the CPU to the GPU, the pointer including a virtual address to a physical memory location in shared memory, the CPU and the GPU to access data at the physical memory location in the shared memory with the same virtual address.

2. The system of claim 1 , wherein:
the pointer is to point to a data structure in the shared memory, wherein the CPU and the GPU are to concurrently operate on the data structure with the virtual address.

3. The system of claim 1 , wherein:
the CPU includes a cache and the GPU includes a second cache, both the cache and the second cache to cache data from the shared memory.

4. The system of claim 1 , further comprising:
an I/O device coupled with the CPU.

5. The system of claim 1 , further comprising:
the shared memory.

6. The system of claim 1 , further comprising:
one or more additional processing units coupled with the CPU, the GPU, and the shared memory.

7. The system of claim 1 , wherein:
the CPU and the GPU are to access data at the physical memory location with the same virtual address through virtual address translation via use of a same page table.

8. A system comprising:
a central processing unit (CPU);
a graphics processing unit (GPU) coupled with the CPU; and
logic to share a pointer from the CPU with the GPU, the pointer including a virtual address to a data structure in shared memory, the CPU and the GPU to simultaneously operate on the data structure with the same virtual address.

9. The system of claim 8 , wherein:
the CPU includes a cache and the GPU includes a second cache, both the cache and the second cache to cache data from the shared memory.

10. The system of claim 8 , further comprising:
the shared memory.

11. The system of claim 8 , further comprising:
one or more additional processing units coupled with the CPU, the GPU, and the shared memory.

12. A non-transitory machine readable medium having stored thereon instructions that, when executed by one or more computing devices, cause the one or more computing devices to:
pass a pointer from a central processing unit (CPU) to a graphics processing unit (GPU), the pointer including a virtual address to a physical memory location in shared memory; and
access data at the physical memory location in the shared memory by both the CPU and the GPU with the same virtual address.

13. The non-transitory machine readable medium of claim 12 , wherein:
the pointer is to point to a data structure in the shared memory, wherein the CPU and the GPU are to concurrently operate on the data structure with the virtual address.

14. The non-transitory machine readable medium of claim 12 , wherein:
the CPU includes a cache and the GPU includes a second cache, both the cache and the second cache to cache data from the shared memory.

Assignees

• Intel Corp

Inventors

• Baxter Brent S
• Hall Clifford D
• Sethi Prashant
• Clifford William H

Classifications

• G06F12/109 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F12/0882

  Page mode · CPC title

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title