Booting a computing system using embedded non-volatile memory

Patent metadata

Field	Value
Publication number	US-10691466-B2
Application number	US-201815943605-A
Country	US
Kind code	B2
Filing date	Apr 2, 2018
Priority date	Apr 2, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Examples include techniques for booting a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores manages a boot process for a computing system.

First claim

What is claimed is:

1. A computing system comprising:
one or more memory modules; and
a processor semiconductor chip, the processor semiconductor chip comprising one or more processing cores; and
a three dimensional cross-point memory coupled to the one or more processing cores, the three dimensional cross-point memory storing BIOS instructions that when executed by the one or more processing cores manages a boot process for the computing system, wherein the BIOS includes instructions to compare information describing the one or more memory modules with information about the one or more memory modules as stored in the three dimensional cross-point memory, and instructions to train the one or more memory modules when the information describing the one or more memory modules does not match the information about the one or more memory modules as stored in the three dimensional cross-point memory wherein instructions to train the one or more memory modules comprise instructions to adjust clocks and data edge and reference voltage levels for reading by sweeping across all possible address ranges, while writing and reading a linear-feedback shift register (LFSR) pattern.

2. The computer system of claim 1 , wherein the BIOS comprises a Unified Extensible Firmware Interface (UEFI) BIOS.

3. The computing system of claim 1 , wherein the information describing one or more memory modules is stored in the three dimensional cross-point memory at time of manufacturing of the computing system.

4. A method comprising:
reading a BIOS from a three dimensional cross-point memory embedded in a processor semiconductor chip having one or more processing cores;
executing the BIOS by the one or more processing cores to boot a computing system;
comparing information describing one or more memory modules installed in the computing system with information about the one or more memory modules as stored in the three dimensional cross-point memory; and
training the one or more memory modules when the information describing the one or more memory modules installed in the computing system does not match the information about the one or more memory modules as stored in the three dimensional cross-point memory, wherein training the one or more memory modules comprises adjusting clocks and data edge and reference voltage levels for reading by sweeping across all possible address ranges, while writing and reading a linear-feedback shift register (LFSR) pattern.

5. The method of claim 4 , wherein the BIOS comprises a Unified Extensible Firmware Interface (UEFI) BIOS.

6. The method of claim 4 , wherein the information describing the one or more memory modules comprises a serial number.

7. The computer system of claim 1 , wherein an instruction format of an instruction set architecture of the processor semiconductor chip's one or more cores includes at least one of an opcode or an immediate operand that specifies memory access is to be directed to the three dimensional cross-point memory.

Assignees

• Intel Corp

Inventors

• Connor Christopher
• Querbach Bruce

Classifications

• G06F9/4405 Primary

  Initialisation of multiprocessor systems · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/4406

  Loading of operating system · CPC title