Charge/discharge control circuit and battery device including the same

Patent metadata

Field	Value
Publication number	US-10686323-B2
Application number	US-201715689520-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Aug 30, 2016
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

Provided are a charge/discharge control circuit capable of using an FET having a low withstand voltage. The charge/discharge control circuit is configured to control charging and discharging of a secondary cell, and includes: a positive power supply terminal and a negative power supply terminal for monitoring a voltage of the secondary cell; a charge control terminal configured to connect to a gate of a charge control FET, the charge control FET having one end connected to an external negative terminal to which a negative electrode of a load or a charger is connected; and a clamp circuit configured to clamp a signal at a high level for turning on the charge control FET to a voltage that is higher than a reference voltage by a predetermined voltage, the reference voltage being a voltage at the external negative terminal, the signal being output to the charge control terminal.

First claim

What is claimed is:

1. A charge/discharge control circuit configured to control charging and discharging of a secondary cell, the charge/discharge control circuit comprising:
a positive power supply terminal and a negative power supply terminal for monitoring a voltage of the secondary cell;
a charge control terminal configured to connect to a gate of a charge control FET, the charge control FET having one end connected to an external negative terminal to which a negative electrode of a charger or a load is connected; and
a first clamp circuit configured to clamp a signal at a high level for turning on the charge control FET to a voltage that is higher than a first reference voltage by a predetermined voltage, the first reference voltage being a voltage at the external negative terminal, the signal at the high level for turning on the charge control FET being output to the charge control terminal.

2. The charge/discharge control circuit according to claim 1 further comprising:
a discharge control terminal configured to connect to a gate of a discharge control FET having one end connected to the other end of the charge control FET; and
a second clamp circuit configured to clamp a signal at a high level for turning on the discharge control FET to a voltage that is higher than a second reference voltage by a predetermined voltage, the second reference voltage being the voltage at the external negative terminal, the signal at the high level for turning on the discharge control FET being output to the discharge control terminal.

3. The charge/discharge control circuit according to claim 2 , further comprising an external negative voltage input terminal configured to connect to the external negative terminal,
wherein both the first reference voltage of the first clamp circuit and the second reference voltage of the second clamp circuit are a voltage that is input to the external negative voltage input terminal.

4. The charge/discharge control circuit according to claim 2 , further comprising an overcurrent detection terminal configured to connect to the other end of the discharge control FET for detecting overcurrent of the secondary cell,
wherein both the first reference voltage of the first clamp circuit and the second reference voltage of the second clamp circuit are a voltage that is input to the overcurrent detection terminal.

5. The charge/discharge control circuit according to claim 1 further comprising:
a discharge control terminal configured to connect to a gate of a discharge control FET having one end connected to the other end of the charge control FET; and
a second clamp circuit configured to clamp a signal at a high level for turning on the discharge control FET to a voltage that is higher than a second reference voltage by a predetermined voltage, the second reference voltage being a voltage at the other end of the discharge control FET, the signal at the high level for turning on the discharge control FET being output to the discharge control terminal.

6. The charge/discharge control circuit according to claim 5 , further comprising:
an external negative voltage input terminal configured to connect to the external negative terminal; and
an overcurrent detection terminal configured to connect to the other end of the discharge control FET for detecting overcurrent of the secondary cell,
wherein the first reference voltage of the first clamp circuit is a voltage that is input to the external negative voltage input terminal and the second reference voltage of the second clamp circuit is a voltage that is input to the overcurrent detection terminal.

7. The charge/discharge control circuit according to claim 5 , further comprising an external negative voltage input terminal configured to connect to the external negative terminal,
wherein the first reference voltage of the first clamp circuit is a voltage that is input to the external negative voltage input terminal and the second reference voltage of the second clamp circuit is a voltage that is input to the negative power supply terminal.

8. The charge/discharge control circuit according to claim 3 ,
wherein the positive power supply terminal is connected to a positive electrode of the charger and the external negative voltage input terminal is connected to the negative electrode of the charger, and
wherein the first clamp circuit and the second clamp circuit are configured to operate when a voltage between the positive power supply terminal and the external negative voltage input terminal becomes a predetermined voltage that is higher than the voltage of the secondary cell.

9. The charge/discharge control circuit according to claim 6 ,
wherein the positive power supply terminal is connected to a positive electrode of the charger and the external negative voltage input terminal is connected to the negative electrode of the charger, and
wherein the first clamp circuit and the second clamp circuit are configured to operate when a voltage between the positive power supply terminal and the external negative voltage input terminal becomes a predetermined voltage that is higher than the voltage of the secondary cell.

10. The charge/discharge control circuit according to claim 2 , further comprising a control terminal configured to receive a signal for controlling operation of the first clamp circuit and operation of the second clamp circuit,
wherein the operation of the first clamp circuit and the operation of the second clamp circuit are stopped when the signal at the control terminal is at a high level.

11. The charge/discharge control circuit according to claim 5 , further comprising a control terminal configured to receive a signal for controlling operation of the first clamp circuit and operation of the second clamp circuit,
wherein the operation of the first clamp circuit and the operation of the second clamp circuit are stopped when the signal at the control terminal is at a high level.

12. A battery device, comprising:
a secondary cell;
an external positive terminal and an external negative terminal to which a load and a charger are connected;
a first charge/discharge control circuit and a second charge/discharge control circuit connected to the secondary cell;
a first charge control FET having one end connected to the external negative terminal;
a first discharge control FET having one end connected to the other end of the first charge control FET;
a second charge control FET having one end connected to the other end of the first discharge control FET; and
a second discharge control FET having one end connected to the other end of the second charge control FET and the other end connected to a negative electrode of the secondary cell,
the first charge/discharge control circuit including:
a positive power supply terminal and a negative power supply terminal for monitoring a voltage of the secondary cell;
a charge control terminal connected to a gate of the first charge control FET; and
a first clamp circuit configured to clamp a signal at a high level for turning on the charge control FET to a voltage that is higher than a first reference voltage by a predetermined voltage, the first reference voltage being a voltage at the external negative terminal, the signal at the high level for turning on the first charge control FET being output to the charge control terminal.

13. The battery device according to claim 12 , wherein the first charge/discharge control circuit further including:
a discharge control terminal connected to a gate of the first discharge control FET; and
a second clamp circuit configured to clamp a signal at a high level for turning on the f

Assignees

• Sii Semiconductor Corp
• Ablic Inc

Inventors

• Sakurai Atsushi
• Ono Takashi

Classifications

• H02J7/977

  of the battery · CPC title

• H02J7/965

  obtained with the battery disconnected from the charge or discharge circuit · CPC title

• H02J7/933

  the cycle being controlled or terminated in response to electric parameters · CPC title

• H02J7/685

  using connection detecting circuits (H02J7/68 takes precedence) · CPC title

• H02J7/667

  disconnection of loads if battery is not under charge, e.g. in vehicle if engine is not running · CPC title