Nano-tube MOSFET technology and devices

Patent metadata

Field	Value
Publication number	US-10686035-B2
Application number	US-201816155066-A
Country	US
Kind code	B2
Filing date	Oct 9, 2018
Priority date	Dec 31, 2008
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

First claim

We claim:

1. A metal oxide semiconductor field effect transistor (MOSFET) comprising:
a semiconductor substrate having a plurality of trenches opened from a top surface;
wherein every two adjacent trenches are separated by a volume of said semiconductor substrate constituting a pillar having a pillar conductivity type;
all sidewalls of each of said trenches are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two opposite sides and substantially symmetrical to a central gap-filler layer disposed between two innermost epitaxial layers is a dielectric layer having a width substantially the same as said plurality of epitaxial layers of alternating conductivity types and significantly smaller than said pillar, and wherein said epitaxial layers of said alternating conductivity types constituting nano tubes functioning as conducting channels extending along a sidewall direction of each of said trenches; and
a body region encompassing source region surrounding a gate of the MOSFET disposed near a top surface of the pillar comprising the volume of the semiconductor substrate for conducting a current through the nano tubes to a drain region disposed on the bottom of the semiconductor substrate.

2. The MOSFET of claim 1 wherein:
said epitaxial layers of the alternating conductivity types in each of said trenches further include an outermost epitaxial layer covers directly on sidewalls of said trenches wherein said outmost epitaxial layer having an opposite conductivity type from said pillar conductivity type; and wherein the nano tubes, and the pillars are substantially charge balanced.

3. The MOSFET of claim 1 wherein:
said pillars between two adjacent trenches with sidewalls covering by said epitaxial layers of the alternating conductivity types have a width approximately half to one-fourth of a width of said trenches and significantly greater than the width of said epitaxial layer of said alternating conductivity and said central gap-filler layer.

4. The MOSFET of claim 1 wherein:
said plurality of trenches each having a width of about ten microns and said plurality of trenches are separated by a said pillar from adjacent trenches wherein said pillar having a width ranging substantially between two to five microns.

5. The MOSFET of claim 1 wherein:
said plurality of trenches each having a width of about ten microns with the sidewalls covered by the epitaxial layers of alternating conductivity types constituting said nano tubes having a layer thickness ranging substantially between about 0.2 to 2 microns and wherein said central gap-filler layer having a layer thickness substantially in a same range as said epitaxial layers of alternating conductivity types.

6. The MOSFET of claim 1 wherein:
said plurality of trenches each having a trench depth ranging substantially between 5 to 120 micrometers.

7. The MOSFET of claim 1 wherein:
said semiconductor substrate further comprising a nano tube merger region comprises a doped layer is disposed below said trenches having sidewalls covered by said nano tubes and below said pillars between said trenches and extended laterally across the semiconductor substrate.

8. The MOSFET of claim 1 wherein:
the sidewalls of said plurality of trenches having a slightly tilted angle relative to a vertical perpendicular direction relative to a bottom surface of said semiconductor substrate.

9. The MOSFET of claim 1 wherein:
said semiconductor substrate comprising a bottom substrate layer of a first conductivity type and said pillars having a second conductivity type.

10. The MOSFET of claim 1 wherein:
said semiconductor substrate comprising a bottom substrate layer of a first conductivity type and said pillars having a same conductivity type with the conductivity type of said bottom substrate layer.

11. The MOSFET of claim 1 wherein:
the pillars constitute the semiconductor volumes comprising a lightly doped epitaxial layer.

12. The MOSFET of claim 1 wherein:
the pillars constitute the semiconductor volumes comprising volumes of a single crystal semiconductor substrate.

13. A metal oxide semiconductor field effect transistor (MOSFET) comprising:
a semiconductor substrate having a plurality of trenches opened from a top surface having slightly tilt sidewalls having a smaller trench bottom area than a top trench opening area; wherein every two adjacent trenches are separated by a volume of said semiconductor substrate constituting a pillar having a pillar conductivity type;
all sidewalls of each of said trenches are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two opposite sides and substantially symmetrical to a central gap-filler layer disposed between two innermost epitaxial layers of an innermost conductivity type as one of said alternating conductivity types wherein said central gap-filler layer is a dielectric layer having a width substantially the same as said plurality of epitaxial layers of alternating conductivity types and significantly smaller than said pillar, and wherein said epitaxial layers of said alternating conductivity types and said central gap-filler layer constituting nano tubes functioning as conducting channels extending along a sidewall direction of each of said trenches; and a body region encompassing source region surrounding a gate of the MOSFET disposed near a top surface of the pillar comprising the volume of the semiconductor substrate for conducting a current through the nano tubes to a drain region disposed on the bottom of the semiconductor substrate.

14. A metal oxide semiconductor field effect transistor (MOSFET) supported on a semiconductor substrate comprising an active cell area having a plurality of MOSFET transistor cells surrounded by a termination area disposed on a peripheral area of the semiconductor substrate wherein the termination area further comprising:
a plurality of trenches opened from a top surface; wherein every two adjacent trenches are separated by a volume of said semiconductor substrate constituting a pillar having a pillar conductivity type;
all sidewalls of each of said trenches are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two opposite sides and substantially symmetrical to a central gap-filler layer disposed between two innermost epitaxial layers wherein the central gap-filler layer having a width substantially the same as said plurality of epitaxial layers of alternating conductivity types and significantly smaller than said pillar, and wherein said epitaxial layers of said alternating conductivity types constituting nano tubes functioning as conducting channels extending along a sidewall direction of each of said trenches;
a plurality of field plates disposed on top of an insulation layer covering a top surface of the semiconductor substrate wherein each of the field plates is connected a top metal layer segment contacting with the top metal layer segments contact a top surface of a body region through openings of the top insulation wherein the body regions are shorted to the plurality of nano tubes.

15. The MOSFET of claim 14 wherein:
the field plates are conductive polysilicon plates.

16. The MOSFET of claim 14 wherein:
said central gap-filler layer comprises a dielectric layer.

17. The MOSFET of claim 14 wherein:
said central gap-filler layer comprises a lightly doped silicon layer.

18. The MOSFET of claim 14 wherein:
one of the top metal layer segments closest to the active cell area is connected

Assignees

• Alpha & Omega Semiconductor

Inventors

• Yilmaz Hamza
• Ng Daniel
• Guan Lingping
• Bhalla Anup
• Ma Wilson
• Ho Moses
• Chen John

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/665

  having edge termination structures · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D30/051

  of FETs having PN junction gates (H10D30/015 takes precedence) · CPC title