Solid-state imaging apparatus and imaging apparatus

Patent metadata

Field	Value
Publication number	US-10685997-B2
Application number	US-201916431302-A
Country	US
Kind code	B2
Filing date	Jun 4, 2019
Priority date	Dec 8, 2016
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

First claim

What is claimed is:

1. A solid-state imaging apparatus, comprising:
a pixel array including a plurality of pixel circuits arranged in a matrix;
a column processor including a column analog-to-digital converter (ADC) disposed for each column of the plurality of pixel circuits to convert an analog pixel signal to a digital pixel signal; and
a test signal generating circuit that generates a first digital signal for testing purposes, wherein
the test signal generating circuit generates the first digital signal within one horizontal scanning period, and
the column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

2. The solid-state imaging apparatus according to claim 1 , wherein
the one horizontal scanning period is included in a vertical blanking interval during imaging.

3. The solid-state imaging apparatus according to claim 1 , wherein
the column processor further includes
a test circuit having the same internal configuration as the column ADC, and
the first analog signal is supplied to the test circuit as a substitute for the analog pixel signal.

4. The solid-state imaging apparatus according to claim 1 , further comprising:
a selector disposed at each column of the plurality of pixel circuits, wherein
the selector selects and outputs one of the analog pixel signal and the first analog signal.

5. The solid-state imaging apparatus according to claim 4 , wherein
the selector selects the first analog signal in the one horizontal scanning period included in the vertical blanking interval during imaging.

6. The solid-state imaging apparatus according to claim 4 , wherein
the selector selects the analog pixel signal in one horizontal scanning period not included in the vertical blanking interval during imaging.

7. The solid-state imaging apparatus according to claim 1 , wherein
the pixel array has a test region including at least one row of the plurality of pixel circuits,
the plurality of pixel circuits each include:
a floating diffusion layer that retains signal charge corresponding to the analog pixel signal; and
a reset transistor that sets a reset potential in the floating diffusion layer, and

the first analog signal is supplied to a drain of the reset transistor.

8. The solid-state imaging apparatus according to claim 7 , wherein
the at least one row of the plurality of pixel circuits in the test region includes a row farthest away from the column processor.

9. The solid-state imaging apparatus according to claim 1 , further comprising:
a digital-to-analog converter (DAC) that converts the first digital signal to the first analog signal and supplies the first analog signal to the pixel array or the column processor as a substitute for the analog pixel signal.

10. The solid-state imaging apparatus according to claim 9 , wherein
the DAC adjusts an output gain of the first analog signal so that the first analog signal does not increase beyond an amplitude of a ramp waveform.

11. The solid-state imaging apparatus according to claim 1 , wherein
the test signal generating circuit increases or decreases the first digital signal for each vertical blanking interval during imaging or each horizontal scanning period in the vertical blanking interval during the imaging.

12. The solid-state imaging apparatus according to claim 1 , wherein
the test signal generating circuit generates:
the first digital signal including a first digital value and a second digital value;
the first digital value during a reset level readout period within the one horizontal scanning period included in the vertical blanking interval; and
the second digital value during a signal level readout period within the one horizontal scanning period included in the vertical blanking interval.

13. The solid-state imaging apparatus according to claim 1 , further comprising:
a determination circuit that determines whether a difference between the first digital signal and the second digital signal is within an expected value range, and
the determination circuit determines that (i) there is no problem when the difference between the first digital signal and the second digital signal is within the expected value range, and (ii) there is a problem when the difference is outside of the expected value range.

14. The solid-state imaging apparatus according to claim 1 , wherein
the test signal generating circuit increases or decreases the first digital signal by a predetermined degree for each vertical blanking interval during imaging or each horizontal scanning period of the vertical blanking interval during the imaging.

15. An imaging apparatus, comprising:
the solid-state imaging apparatus according to claim 1 ; and
any one of a view system, an advanced driver-assistance sensing system, and an automated driving sensing system.

16. The imaging apparatus according to claim 15 , wherein
the imaging apparatus is installed on at least one of a front-view mirror, a left side mirror, a right side mirror, and a rear-view mirror of transportation machinery.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Ikuma Makoto
• Amikawa Hiroyuki
• Kito Takayasu
• Ogita Shinichi
• Matsuo Junichi
• Endoh Yasuyuki
• Tokuyama Katsumi
• Abe Tetsuya

Classifications

• H04N23/54

  Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils · CPC title

• H04N25/57

  Control of the dynamic range · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N23/73

  by influencing the exposure time · CPC title

• H04N25/583

  with different integration times · CPC title