Packaging device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10685904-B2
Application number	US-201414549996-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Nov 21, 2014
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

First claim

What is claimed is:

1. A packaging device, comprising:
a first semiconductor device comprising a substrate, an active region, and an electrode, the active region is disposed between the substrate and the electrode, the substrate having a first surface opposite to the active region, and the electrode having a second surface opposite to the active region;
a thermal dissipating component disposed on the first surface of the substrate, wherein a thickness of the thermal dissipating component and a width of the thermal dissipating component are larger than those of the first semiconductor device, and a contact area between the thermal dissipating component and the substrate is substantially the same as an area of the first surface;
an encapsulation layer enclosing the second surface of the electrode and a part of the thermal dissipating component, wherein the thermal dissipating component comprises a third surface and a fourth surface facing toward a direction away from the first semiconductor device, the third surface is exposed by the encapsulation layer, the fourth surface is covered by the encapsulation layer, and wherein the encapsulation layer comprises a fifth surface facing the thermal dissipating component and opposite to the fourth surface, and the fifth surface is only in contact with the thermal dissipating component;
a pad disposed on the encapsulation layer; and
a via disposed in the encapsulation layer, wherein the via connects the pad to the electrode.

2. The packaging device of claim 1 , wherein a thickness of the thermal dissipating component is greater than a thickness of the pad.

3. The packaging device of claim 1 , wherein a quantity of heat dissipation passing through the first surface of the substrate is greater than a quantity of heat dissipation passing through the second surface of the electrode.

4. The packaging device of claim 1 , wherein the active region and the electrode form a GaN transistor.

5. The packaging device of claim 1 , further comprising a solder disposed between the first semiconductor device and the thermal dissipating component.

6. The packaging device of claim 5 , wherein the solder is made from metal.

7. The packaging device of claim 1 , wherein the electrode of the first semiconductor device is spatially separated from the thermal dissipating component.

8. The packaging device of claim 1 , wherein the thermal dissipating component comprises a first portion and a second portion separated from each other, the first portion is disposed on the first semiconductor device, the packaging device further comprises a second semiconductor device, and the second portion is disposed thereon.

9. The packaging device of claim 8 , wherein the first portion of the thermal dissipating component has a cavity for accommodating the first semiconductor device.

10. The packaging device of claim 8 , wherein a thickness of the first semiconductor device is different from a thickness of the second semiconductor device.

11. The packaging device of claim 10 , wherein the second surface of the first semiconductor device and a surface of the second semiconductor device opposite to the thermal dissipating component are coplanar.

12. The packaging device of claim 8 , further comprising:
a third semiconductor device electrically connected to the first portion and the second portion of the thermal dissipating component.

Assignees

• Delta Electronics Inc

Inventors

• Tsai Hsin-Chang
• Lee Chia-Yen
• Lee Peng-Hsin

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title