Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices

Patent metadata

Field	Value
Publication number	US-10683205-B2
Application number	US-201816101353-A
Country	US
Kind code	B2
Filing date	Aug 10, 2018
Priority date	Sep 4, 2014
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

First claim

What is claimed is:

1. An integrated device, comprising:
a complementary metal-oxide-semiconductor (CMOS) wafer; and
a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer, wherein the MEMS device comprises sacrificial layer that is removable by utilization of a release chemical, wherein the release chemical comprises hydrofluoric acid, and wherein the CMOS wafer comprises a passivation layer with an opening having a sidewall that exposes a dielectric layer of the CMOS wafer and a barrier material, comprising a metal resistant to the release chemical, that covers the sidewall, wherein the passivation and the dielectric layer are distinct layers comprising different materials, wherein the barrier material is a first barrier material wherein a second barrier layer is provided over at least a portion of the first barrier material, and wherein the metal comprises Aluminum.

2. The integrated device of claim 1 , wherein the barrier material is formed by depositing the metal on the integrated circuit substrate and patterning the metal to leave a portion of the metal that forms the barrier layer on the sidewall.

3. The integrated device of claim 2 , wherein the depositing comprises depositing the barrier material based on sputtering.

4. The integrated device of claim 2 , wherein the depositing comprises depositing the barrier material based on evaporation.

5. The integrated device of claim 2 , wherein the depositing comprises depositing the barrier material based on atomic layer deposition.

6. The integrated device of claim 2 , wherein the depositing comprises depositing the barrier material based on plasma enhanced chemical vapor deposition.

7. The integrated device of claim 2 , wherein the depositing comprises depositing the barrier material based on a low pressure chemical vapor deposition process.

8. The integrated device of claim 1 , wherein the release chemical comprises vapor-phase hydrofluoric acid.

9. The integrated device of claim 1 , wherein the release chemical comprises liquid-phase hydrofluoric acid.

10. The integrated device of claim 1 , wherein the second barrier material comprises an insulator.

11. The integrated device of claim 1 , wherein the second barrier material comprises a dielectric material.

12. An integrated device, comprising:
a complementary metal-oxide-semiconductor (CMOS) wafer; and
a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer, wherein the MEMS device comprises sacrificial layer that is removable by utilization of a release chemical, wherein the release chemical comprises hydrofluoric acid, and wherein the CMOS wafer comprises a passivation layer with an opening having a sidewall that exposes a dielectric layer of the CMOS wafer and a barrier material, comprising a metal resistant to the release chemical, that covers the sidewall, wherein the passivation and the dielectric layer are distinct layers comprising different materials, wherein the barrier material is a first barrier material, wherein a second barrier layer is provided over at least a portion of the first barrier material, and wherein the second barrier material comprises an insulator.

13. The integrated device of claim 12 , wherein the barrier material is formed by depositing the metal on an integrated circuit substrate and patterning the metal to leave a portion of the metal that forms the barrier layer on the sidewall.

14. The integrated device of claim 13 , wherein the depositing comprises depositing the barrier material based on at least one of sputtering, evaporation, atomic layer deposition or plasma enhanced chemical vapor deposition.

15. The integrated device of claim 13 , wherein the depositing comprises depositing the barrier material based on a low pressure chemical vapor deposition process.

16. The integrated device of claim 12 , wherein the release chemical comprises at least one of vapor-phase hydrofluoric acid or liquid-phase hydrofluoric acid.

Assignees

• Invensense Inc

Inventors

• Daneman Michael J
• Assaderaghi Fariborz

Classifications

• B81C1/00801 Primary

  Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer (B81C1/00595, B81C1/00468 take precedence) · CPC title

• B81C2201/0133

  Wet etching · CPC title

• B81C2201/0132

  Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling · CPC title

• B81C2201/053

  Depositing a protective layers · CPC title

• B81C1/00539

  Wet etching · CPC title