Semiconductor device and operating method thereof

Patent metadata

Field	Value
Publication number	US-10680923-B2
Application number	US-201715427522-A
Country	US
Kind code	B2
Filing date	Feb 8, 2017
Priority date	Feb 11, 2016
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A semiconductor device and an operating method thereof are provided. An operating method of a semiconductor device, includes monitoring a plurality of request packets and a plurality of response packets that are being transmitted between a master device and a slave device; detecting a target request packet that matches desired identification (ID) information from among the plurality of request packets; counting the number of events of a transaction including the target request packet by using an event counter; counting the number of request packets whose corresponding response packets are yet to be detected, from among the plurality of request packets by using a Multiple Outstanding (MO) counter, determining whether an MO count value of the MO counter is valid; and if the MO count value is invalid, resetting the event counter.

First claim

What is claimed is:

1. An operating method of a semiconductor device, comprising:
monitoring a plurality of request packets and a plurality of response packets transmitted between at least one master device and at least one slave device, the at least one master device and the at least one slave device included in the semiconductor device;
detecting a target request packet that matches desired identification (ID) information from among the plurality of request packets;
counting a number of events of a transaction based on the target request packet using an event counter;
counting a number of request packets whose corresponding response packets have not been detected from among the plurality of request packets using a Multiple Outstanding (MO) counter;
determining whether an MO count value of the MO counter is valid; and
in response to the MO count value being invalid, resetting the event counter.

2. The operating method of claim 1 , wherein the resetting the event counter comprises resetting the MO counter.

3. The operating method of claim 1 , wherein the desired ID information includes at least one of transaction ID information and transaction attribute information.

4. The operating method of claim 3 , wherein the transaction ID information includes unique ID information for identifying the at least one master device or the at least one slave device.

5. The operating method of claim 3 , wherein the transaction attribute information includes at least one of burst length attribute information and cache snooping type attribute information.

6. The operating method of claim 1 , wherein:
the at least one master device is an Intellectual Property (IP) block provided in a System-on-Chip (SoC); and
the at least one master device and the at least one slave device exchange the plurality of request packets and the plurality of response packets via an On-Chip Interconnect (OCI).

7. The operating method of claim 6 , further comprising:
receiving the desired ID information, the desired ID information being set by a user or an application external to the SoC.

8. The operating method of claim 1 , further comprising:
acquiring a first latency value of a first transaction and a second latency value of a second transaction, the second transaction being different from the first transaction; and
computing an average latency and a peak latency based on the first latency value and the second latency value.

9. The operating method of claim 8 , further comprising:
debugging a channel between the at least one master device and the at least one slave device by using the average latency and the peak latency.

10. The operating method of claim 9 , further comprising:
controlling a Quality-of-Service (QoS) of the channel based on the average latency and the peak latency.

11. An operating method of a semiconductor device, comprising:
monitoring a plurality of request packets and a plurality of response packets between a first intellectual property (IP) block and a second IP block, the first IP block and second IP block included in a System-on-Chip (SoC);
receiving desired first ID information and desired second ID information;
counting a number of events of a first transaction from the plurality of request packets and the plurality of response packets that matches the desired first ID information using an event counter;
counting a number of events of a second transaction from the plurality of request packets and the plurality of response packets that that matches the desired second ID information using the event counter;
counting a number of outstanding request packets whose corresponding response packets have not been detected from among the plurality of request packets by using Multiple Outstanding (MO)counter;
determining whether an MO count value of the MO counter is valid; and
in response to the MO count value being invalid, resetting the event counter.

12. The operating method of claim 11 , wherein the resetting the event counter comprises resetting the MO counter.

13. The operating method of claim 11 , wherein the desired ID information includes at least one of transaction ID information and transaction attribute information.

14. The operating method of claim 13 , wherein the transaction ID information includes unique ID information for identifying the first IP block or the second IP block.

15. The operating method of claim 13 , wherein the transaction attribute information includes at least one of burst length attribute information and cache snooping type attribute information.

16. A method of monitoring a channel of a semiconductor device, comprising:
sampling packet transmissions over the channel of the semiconductor device, the packet transmissions including a plurality of request packets and a plurality of response packets;
detecting whether a request packet from the sampled plurality of request packets matches a target request packet based on a desired transaction ID;
detecting whether a response packet from the sampled plurality of response packets matches a target response packet based on the desired transaction ID;
updating a count of a number of transaction events completed based on the detecting of the request packet and the detecting of the response packet;
determining whether the count of the number of transaction events completed is valid; and
outputting the count of the number of transaction events to a debugging destination based on results of the determining.

17. The method of claim 16 , wherein
the determining includes determining that the count of the number of transaction events is valid if the count is greater than or equal to 0; and
the outputting includes resetting the count of the number of transaction events completed if the count of the number of transaction events completed is invalid.

18. The method of claim 16 , wherein
the channel includes at least a first intellectual property (IP) block and a second IP block; and
the sampling includes monitoring packet transmissions between the first IP block and the second IP block.

19. The method of claim 16 , further comprising:
measuring a time between the detecting the request packet that matches the target request packet and the detecting the response packet that matches the target response packet; and
determining a latency associated with the channel based on the measured time.

20. The method of claim 19 , wherein the outputting includes resetting the count of the number of transaction events completed and a latency measurement, if the count of the number of transaction events completed is invalid.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Jae Geun
• Jo Seong Min
• Cho Yun Kyo
• Kim Byeong Jin
• Kang Dong Soo
• Seong Nak Hee

Classifications

• H04L43/0876

  Network utilisation, e.g. volume of load or congestion level · CPC title

• H04L41/06

  Management of faults, events, alarms or notifications · CPC title

• H04L43/0858 Primary

  One way delays · CPC title

• G06F5/08 Primary

  having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register {(G06F5/065 takes precedence; shift registers per se G11C19/00)} · CPC title