Quadrature signal generation

Patent metadata

Field	Value
Publication number	US-10680795-B2
Application number	US-201916424743-A
Country	US
Kind code	B2
Filing date	May 29, 2019
Priority date	Oct 9, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Apparatuses and methods for quadrature signal generation are provided. An example includes a quadrature signal generator. The quadrature signal generator is configured to generate, based on a received differential signal, a plurality of quadrature clock signals at a same frequency as that of the received differential signal. The quadrature signal generator is also configured to provide the plurality of quadrature clock signals to a memory system.

First claim

What is claimed is:

1. An apparatus, comprising:
a quadrature signal generator configured to:
generate, based on a received differential signal having a non-sinusoidal waveform, a plurality of quadrature signals at a same frequency as that of the received differential signal;
convert, to generate a plurality of quadrature clock signals, the plurality of quadrature signals to a sinusoidal waveform; and
provide the plurality of quadrature clock signals to a memory system;

wherein the quadrature signal generator comprises a filter bank and is configured to use the filter bank to generate the plurality of quadrature clock signals;
wherein:
the filter bank is one of a plurality of components included in the quadrature signal generator; and
at least one of the plurality of components comprises a capacitor bank whose constituent capacitors are controllable by respective control bits.

2. The apparatus of claim 1 , wherein the differential signal is received from a clock generator coupled to the quadrature signal generator.

3. The quadrature signal generator of claim 2 , wherein the clock generator comprises a phase locked loop (PLL).

4. A quadrature signal generator, comprising:
a polyphase filter configured to generate, in response to receipt of a differential signal from a clock generator, a plurality of quadrature signals having a sinusoidal waveform at a same frequency as that of the differential signal; and
wherein the quadrature signal generator is configured to convert, to generate a plurality of quadrature clock signals, the plurality of quadrature signals to a non-sinusoidal waveform;
wherein the quadrature signal generator further comprises a smoothing filter, and the quadrature signal generator is configured to use the smoothing filter to:
convert the received differential signal to a sinusoidal waveform; and
provide, to the polyphase filter, the differential signal having the converted sinusoidal waveform and a bias voltage.

5. The quadrature signal generator of claim 4 , further comprising a duty cycle adjuster coupled to the clock generator, and wherein:
the quadrature signal generator is configured to use the duty cycle adjuster to adjust, via an adjustable capacitive load, rise/fall time of the differential signal received from the clock generator.

6. The quadrature signal generator of claim 4 , wherein:
the quadrature signal generator is configured to use the smoothing filter to change, to convert the differential signal to the sinusoidal waveform, a slew rate of the differential signal until the differential signal is converted to the sinusoidal waveform.

7. The quadrature signal generator of claim 4 , wherein the smoothing filter comprises a capacitor bank whose constituent capacitors are controllable by respective control bits, and wherein the smoothing filter is configured to control the constituent capacitors of the capacitor bank to change a slew rate of the differential signal until the differential signal is converted to the sinusoidal waveform.

8. The quadrature signal generator of claim 4 , wherein the polyphase filter is a multi-stage polyphase filter, in which at least one of a plurality of stages of the polyphase filter comprises a symmetric resistor-capacitor (RC) network.

9. The quadrature signal generator of claim 4 , further comprising a limiting amplifier, and wherein the quadrature signal generator is configured to convert, to the non-sinusoidal waveform, the plurality of quadrature signals via the limiting amplifier.

10. A method, comprising:
in response to receiving, from a clock generator, a differential signal having a non-sinusoidal waveform:
generating, at a filter bank, a plurality of quadrature signals having a sinusoidal waveform at a same frequency as that of the differential signal; and
generating, based on the plurality of quadrature signals, a plurality of quadrature clock signals by converting the plurality of quadrature signals to a non-sinusoidal waveform,

wherein the method further comprises providing, to the filter bank:
the differential signal having the converted sinusoidal waveform; and
a pair of signals corresponding to respective DC bias voltages that are complementary to one another.

11. The method of claim 10 , further comprising converting the differential signal to the sinusoidal waveform prior to providing the differential signal to the filter bank.

12. The method of claim 11 , wherein converting the differential signal to the sinusoidal waveform comprises changing a slew rate of the differential signal until the differential signal is converted to the sinusoidal waveform.

13. The method of claim 11 , wherein converting the differential signal to the sinusoidal waveform comprises controlling, via respective control bits, constituent capacitors of a capacitor bank to change a slew rate of the differential signal.

14. The method of claim 10 , wherein the non-sinusoidal waveform is a square waveform, and wherein the method further comprises providing the plurality of quadrature clock signals to a memory system.

15. A quadrature signal generator, comprising:
a polyphase filter configured to generate, in response to receipt of a differential signal from a clock generator, a plurality of quadrature signals having a sinusoidal waveform at a same frequency as that of the differential signal; and
wherein the quadrature signal generator is configured to convert, to generate a plurality of quadrature clock signals, the plurality of quadrature signals to a non-sinusoidal waveform; and
wherein the quadrature signal generator further comprises a duty cycle adjuster coupled to the clock generator, and wherein the quadrature signal generator is configured to use the duty cycle adjuster to adjust, via an adjustable capacitive load, rise/fall time of the differential signal received from the clock generator.

16. A quadrature signal generator, comprising:
a polyphase filter configured to generate, in response to receipt of a differential signal from a clock generator, a plurality of quadrature signals having a sinusoidal waveform at a same frequency as that of the differential signal; and
wherein the quadrature signal generator is configured to convert, to generate a plurality of quadrature clock signals, the plurality of quadrature signals to a non-sinusoidal waveform;
wherein the quadrature signal generator further comprises a limiting amplifier, and wherein the quadrature signal generator is configured to convert, to the non-sinusoidal waveform, the plurality of quadrature signals via the limiting amplifier.

17. A quadrature signal generator, comprising:
a polyphase filter configured to generate, in response to receipt of a differential signal from a clock generator, a plurality of quadrature signals having a sinusoidal waveform at a same frequency as that of the differential signal; and
wherein the quadrature signal generator is configured to convert, to generate a plurality of quadrature clock signals, the plurality of quadrature signals to a non-sinusoidal waveform;
wherein the quadrature signal generator further comprises a phase adjuster coupled to the limiting amplifier, and wherein the quadrature signal generator is configured use the phase adjuster to change, to correct a phase error between an in-phase (I) signal and a quadrature (Q) signal of the plurality of quadrature signals, a slew rate of the plurality of quadrature signals.

18. The quadrature signal generator of claim 17 , wherein the phase adjuster comprises a capacitor bank whose constituent capacitors are cont

Assignees

• Micron Technology Inc

Inventors

• Cai Liuchun
• Wurzer Steven G
• King Gregory A

Classifications

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H04L7/04 Primary

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H03B27/00 Primary

  Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs · CPC title

• H03H7/21

  providing two or more phase shifted output signals, e.g. n-phase output · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title