Event activity trigger

Patent metadata

Field	Value
Publication number	US-10680588-B2
Application number	US-201614995008-A
Country	US
Kind code	B2
Filing date	Jan 13, 2016
Priority date	Jan 13, 2016
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Methods of triggering a test and measurement instrument having a plurality of inputs include the step of generating a trigger signal in response to every occurrence of any one of a plurality of specified trigger events. A first specified trigger event occurs in at least a first one of the inputs and a second specified trigger event occurs in at least a second one of the plurality of inputs. A specified trigger event may include at least one selected input from the plurality of inputs and a selected activity type. Some methods include configuring each of a plurality of event activity detectors to produce a pulse in a logic signal in response to every occurrence of one of the specified trigger events. The plurality of logic signals are combined in a logical OR circuit to generate the trigger signal. Trigger circuits configured according to these methods are also disclosed.

First claim

What is claimed is:

1. A method of triggering a test and measurement instrument having a plurality of inputs, the method comprising the step of:
generating a trigger signal that causes the instrument to trigger in response to every occurrence of any one of a plurality of specified trigger events,
in which a first one of the plurality of specified trigger events occurs in at least a first one of the plurality of inputs and a second one of the plurality of specified trigger events occurs in at least a second one of the plurality of inputs, and
in which the trigger signal is generated asynchronously.

2. The method according to claim 1 in which the step of generating the trigger signal comprises:
receiving a first trigger event specification; and
receiving a second trigger event specification,
in which the first and second trigger event specifications each comprise at least one selected input from the plurality of inputs and a selected activity type.

3. The method according to claim 2 in which one of the selected activity types is selected from the group consisting of rising edge, falling edge, either edge, setup and hold, window, pulse width, glitch, runt, timeout, transition time, pattern, frequency, period, bus, envelope, and serial.

4. The method according to claim 2 , further comprising:
configuring a first event activity detector to produce a first logic signal in response to every occurrence of an event meeting the first trigger event specification; and
configuring a second event activity detector to produce a second logic signal in response to every occurrence of an event meeting the second trigger event specification.

5. The method according to claim 4 , further comprising:
combining the first and second logic signals in a logical OR circuit to generate the trigger signal,
in which the first and second trigger event activity detectors are each configured to produce a pulse in, respectively, the first and second logic signals.

6. The method according to claim 5 in which the pulses in the first and second logic signals are produced in such a way that the pulses do not overlap in time.

7. The method according to claim 4 , further comprising:
providing the first logic signal as the clock input of a first flip-flop;
providing the second logic signal as the clock input of a second flip-flop;
providing a hold-off signal as the Reset input of both the first and second flip-flops; and
combining the outputs of the first and second flip-flops in a logical OR circuit to generate the trigger signal, in which the trigger signal is conditioned by the hold-off signal.

8. A test and measurement instrument comprising:
a trigger circuit configured to perform the method of claim 1 .

9. The test and measurement instrument according to claim 8 in which the trigger circuit operates in continuous time.

10. The test and measurement instrument according to claim 8 in which the trigger circuit comprises:
a first event activity detector having a first input and being structured to generate a pulse in a first logic signal in response to every occurrence of a first selected activity type occurring in at least the first input;
a second event activity detector having a second input and being structured to generate a pulse in a second logic signal in response to every occurrence of a second selected activity type occurring in at least the second input; and
a logical OR circuit having the first and second logic signals as inputs and producing the trigger signal as an output.

11. The test and measurement instrument according to claim 10 in which the first and second selected activity types are each selected from the group consisting of rising edge, falling edge, either edge, setup and hold, window, pulse width, glitch, runt, timeout, transition time, pattern, frequency, period, bus, envelope, and serial.

12. The test and measurement instrument according to claim 8 in which the trigger circuit comprises:
a first event activity detector having a first input and being structured to generate an active state of a first logic signal in response to every occurrence of a first selected activity type occurring in at least the first input;
a second event activity detector having a second input and being structured to generate an active state of a second logic signal in response to every occurrence of a second selected activity type occurring in at least the second input;
a first flip-flop having the first logic signal as the clock input and a hold-off signal as the Reset input;
a second flip-flop having the second logic signal as the clock input and the hold-off signal as the Reset input; and
a logical OR circuit having the outputs of the first and second flip-flops as inputs, and producing the trigger signal as an output, in which the trigger signal is conditioned by a hold-off period.

13. The test and measurement instrument according to claim 12 in which the first and second selected activity types are selected from the group consisting of rising edge, falling edge, either edge, setup and hold, window, pulse width, glitch, runt, timeout, transition time, pattern, frequency, period, bus, envelope, and serial.

Assignees

• Tektronix Inc

Inventors

• Smith Patrick A
• Knierim Daniel G

Classifications

• G01R13/0254 Primary

  for triggering, synchronisation · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K3/037 Primary

  Bistable circuits · CPC title