Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10680080-B2
Application number	US-201816162962-A
Country	US
Kind code	B2
Filing date	Oct 17, 2018
Priority date	Jun 14, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A method for manufacturing a semiconductor device includes forming a gate insulation film and a polysilicon layer on a substrate, forming a polysilicon pattern by etching the polysilicon layer, forming an opening in the polysilicon pattern that exposes a part of the polysilicon pattern by forming a mask pattern on the polysilicon pattern, forming a gate electrode by etching the part of the polysilicon pattern exposed through the opening, forming a P-type body region by ion implanting a P-type dopant onto the substrate using the gate electrode as a mask, forming an N-type LDD region on the P-type body region by ion implanting an N-type dopant onto the substrate using the gate electrode as a mask, forming a spacer on a side surface of the gate electrode, and forming an N-type source region on a side surface of the spacer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a gate insulation film and a polysilicon layer on a substrate;
forming a polysilicon pattern by etching the polysilicon layer;
forming a mask pattern on the polysilicon pattern to expose a portion of the polysilicon pattern;
performing a first ion implantation process that implants dopants that pass through the exposed polysilicon pattern to form a first body ion implantation region;
forming a gate electrode by etching the exposed polysilicon pattern;
forming a spacer on a side surface of the gate electrode; and
forming an N-type source region on a side surface of the spacer.

2. The method of claim 1 , further comprising a secondary ion implantation process onto the substrate using the gate electrode as a mask to form a second body ion implantation region, wherein a P-type body region comprises the first and second body ion implantation regions.

3. The method of claim 2 , wherein the second body ion implantation region is formed by tilted ion implantation.

4. The method of claim 2 , wherein the P-type body region is formed to overlap with the gate electrode.

5. The method of claim 2 , wherein the P-type body region has a longer width as it becomes closer to a top surface of the substrate.

6. The method of claim 2 , wherein the first body ion implantation region has a depth deeper than a depth of the second body ion implantation region.

7. The method of claim 2 , wherein the N-type source region is formed in the P-type body region.

8. The method of claim 1 , wherein the forming the gate electrode comprises forming a first gate electrode and a second gate electrode spaced apart from each other.

9. The method of claim 1 , further comprising:
forming an N-type buried layer, a P-type buried layer, and an N-type drift region in the substrate;
forming a P-type well region connected to the P-type buried layer; and
forming an N-type well region connected to the N-type buried layer.

10. The method of claim 9 , wherein the N-type buried layer has a length that is greater than a length of the P-type buried layer.

11. The method of claim 9 , wherein the first body ion implantation region is in direct contact with the P-type buried layer.

12. The method of claim 1 , wherein the gate electrode is formed of polysilicon, tungsten (W), tungsten nitride (WN), titanium (Ti), molybdenum (Mo), cobalt (Co), nickel (Ni), copper (Cu), or aluminum (Al).

13. The method of claim 1 , wherein the gate insulation film is formed of any one or any combination of any two or more of silicon oxide film (SiO 2 ) or a silicon nitride film (SiN), a silicon oxide nitride film (SiON), and a high-k material film.

14. The method of claim 13 , wherein the high-k material film comprises any one or any combination of any two or more of aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 5 ), and hafnium oxide (HfO 2 ).

15. A method for manufacturing a semiconductor device, comprising:
forming a gate insulation film and a polysilicon layer on a substrate;
forming a mask pattern on the polysilicon layer;
performing a first ion implantation process, using a P-type dopant, onto the substrate, that implants the P-type dopant that passes through the polysilicon layer;
forming a gate electrode by etching the polysilicon layer using the mask pattern;
forming a P-type body region in the substrate that overlaps the gate electrode by performing secondary ion implantation onto the substrate, using the gate electrode as a mask;
forming an N-type LDD region in the P-type body region, using the gate electrode as a mask;
forming a spacer on the gate electrode; and
forming an N-type source region in the P-type body region.

16. The method of claim 15 , further comprising forming an N-type drain region spaced apart from the gate electrode.

17. The method of claim 15 , further comprising forming a P-type buried layer that contacts the P-type body region before forming the gate insulation film and the polysilicon layer on the substrate.

18. A semiconductor device comprising:
a first conductivity type buried layer formed on a substrate;
a second conductivity type buried layer formed on the first conductivity type buried layer and having a width that is less than a width of the first conductivity type buried layer;
first conductivity type first and second drift regions formed on the second conductivity type buried layer;
first and second gate electrodes formed on the first and second drift regions, respectively;
a second conductivity type body region disposed between the first and second drift regions and connected to the second conductivity type buried layer; and
a first conductivity type source region disposed between the first and second drift regions and formed on the second conductivity type body region.

19. The semiconductor device of claim 18 , further comprising first and second drain regions of the first conductivity type formed spaced apart from the first and second gate electrode, respectively.

20. The semiconductor device of claim 18 , wherein the body region comprises a plurality of body ion implantation regions having different depths.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Lee Tae Hoon
• Cho Jun Hee
• Chung Jin Seong

Classifications

• H01L29/1083

  Electricity · mapped topic

• H01L29/0634

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/4175

  Electricity · mapped topic

• H01L29/66659 Primary

  Electricity · mapped topic