Trench gate manufacturing method

Patent metadata

Field	Value
Publication number	US-10680070-B2
Application number	US-201816142355-A
Country	US
Kind code	B2
Filing date	Sep 26, 2018
Priority date	Sep 29, 2017
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A trench gate manufacturing method includes the following steps: Step 1, forming a trench in the surface of a semiconductor substrate; Step 2, forming a first oxide layer; Step 3, selecting a coating according to the depth-to-width ratio of the trench and forming the coating completely filling the trench; Step 4, etching back the coating through a dry etching process; Step 5, conducting wet etching on the first oxide layer with the coating reserved at the bottom of the trench as a mask so as to form a gate bottom oxide; Step 6, removing the coating; and Step 7, growing a gate oxide. By adoption of the trench gate manufacturing method, a BTO can be realized at a low cost, and can be well-formed in trenches with smaller depth-to-width ratios and thus is suitable for forming BTOs in trenches with various depth-to-width ratios, thereby having a wider application range.

First claim

What is claimed is:

1. A trench gate manufacturing method, comprising the following steps:
Step 1, forming a trench in a surface of a semiconductor substrate;
Step 2, forming a first oxide layer on a bottom surface, a side surface and an outer surface of the trench, wherein the first oxide layer has a thickness equal to a thickness of a gate bottom oxide;
Step 3, selecting a coating according to a depth-to-width ratio of the trench and then forming the coating on a surface of the first oxide layer, the coating is a GF70 bottom anti-reflection coating, wherein the coating has a flowability meeting conditions where the trench is completely filled by the coating and where a thickness difference between a portion, located outside the trench, of the coating and a portion, located inside the trench, of the coating is greater than a height of the subsequently-obtained gate bottom oxide located on a side surface of the trench;
Step 4, etching back the coating through a dry etching process until the portion, located outside the trench, of the coating is etched away and the portion, located inside the trench, of the coating is etched to a depth required for forming the gate bottom oxide;
Step 5, conducting wet etching on the first oxide layer with the coating reserved at a bottom of the trench as a mask until the first oxide layer is only reserved at the bottom of the trench and the gate bottom oxide is formed;
Step 6, removing the coating; and
Step 7, growing a gate oxide, wherein the gate oxide is located on the side surface, above the gate bottom oxide, of the trench and has a thickness smaller than the thickness of the gate bottom oxide.

2. The trench gate manufacturing method according to claim 1 , wherein the trench gate manufacturing method further comprises the following step:
Step 8, filling the trench with a gate electrode material layer.

3. The trench gate manufacturing method according to claim 2 , wherein the gate electrode material layer is a polysilicon gate.

4. The trench gate manufacturing method according to claim 2 , wherein a trench gate is a gate structure of an MOS transistor, and the trench gate manufacturing method further comprises the following steps:
Step 9, forming a channel region, wherein the channel region has a depth smaller than a depth of the gate oxide, the polysilicon gate covers the channel region via a side surface of the gate oxide, and a channel is formed in a surface of the channel region covered by a side surface of the polysilicon gate; and the semiconductor substrate is doped to be of a first conduction type, and the channel region is doped to be of a second conduction type;
Step 10, forming a heavily-doped source region of the first conduction type on a surface of the channel region; and
Step 11, forming a heavily-doped drain region of the first conduction type on a back side of the semiconductor substrate.

5. The trench gate manufacturing method according to claim 4 , wherein the MOS transistor is an NMOS transistor, the first conduction type is an N type, and the second conduction type is a P type; or, the MOS transistor is a PMOS transistor, the first conduction type is a P type, and the second conduction type is an N type.

6. The trench gate manufacturing method according to claim 1 , wherein the semiconductor substrate is a silicon substrate.

7. The trench gate manufacturing method according to claim 6 , wherein the first oxide layer is made from silicon oxide, and the gate oxide is also made from silicon oxide.

8. The trench gate manufacturing method according to claim 7 , wherein the first oxide layer is formed through a thermal oxidization process in Step 2; or, the first oxide layer is formed through a chemical vapor deposition process in Step 2.

9. The trench gate manufacturing method according to claim 7 , wherein the gate oxide is formed through a thermal oxidization process.

10. The trench gate manufacturing method according to claim 1 , wherein the trench has various depth-to-width ratios, and the flowability of the coating meets the conditions where a trench with the minimum depth-to-width ratio is completely filled by the coating and a thickness difference between a portion, located outside the trench with the minimum depth-to-width ratio, of the coating and a portion, located inside the trench with the minimum depth-to-width ratio, of the coating is greater than the height of the subsequently-obtained gate bottom oxide located on the side surface of the trench.

11. The trench gate manufacturing method according to claim 1 , wherein the drying etching in Step 4 is isotropic etching or anisotropic etching.

Assignees

• Shanghai Huahong Grace Semiconductor Mfg Corp

Inventors

• Yang Jiye
• Li Hao
• Wang Lei
• Zhao Longjie
• Sun Xiaoxiang

Classifications

• H01L21/31116

  Electricity · mapped topic

• H01L29/66613

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic