Timing controller, display apparatus having the same and signal processing method thereof

Patent metadata

Field	Value
Publication number	US-10679546-B2
Application number	US-201815948483-A
Country	US
Kind code	B2
Filing date	Apr 9, 2018
Priority date	Feb 13, 2008
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A timing controller includes a count control circuit, a pulse width detector, and a pulse generator. The count control circuit receives an external enable signal. Pulses of the external enable signal include an effective and a blank period of image data. The count control circuit counts pulse widths of each of the pulses. The pulse width detector receives the counted pulse widths, compares a pulse width of a present pulse with pulse widths of previous pulses, and detects a pulse width of a previous pulse that has a pulse width smaller than the pulse width of the present pulse. The pulse generator generates three output pulses having pulse widths that are one-third a period of the detected previous pulse. The pulse generator outputs the first, second and third pulses as an internal enable signal.

First claim

What is claimed is:

1. A timing controller comprising:
a count control circuit configured to receive a first enable signal, the first enable signal including a first input pulse and a plurality of second input pulses, wherein the second input pulses are provided to the count control circuit prior to the first input pulse being provided to the count control circuit, the second input pulses are consecutive, the first input pulse is consecutive to a last input pulse of the second input pulse, and the count control circuit is configured to determine a first period of the first input pulse and second periods of the second input pulses;
a pulse width detector configured to compare each of the second periods against the first period to identify one period among the second periods that is smaller than the first period; and
a pulse generator configured to generate each of a first output pulse, a second output pulse and a third output pulse, after the first input pulse has been provided to the count control circuit, wherein a period of each of the first output pulse, the second output pulse, and the third output pulse, is one-third a period of the identified one period, wherein the pulse generator outputs the first output pulse, the second output pulse and the third output pulse as a second enable signal, and the and the first output pulse, the second output pulse and the third output pulse are consecutive, wherein the first enable signal is provided by a source external to the timing controller and the second enable signal is generated within the timing controller.

2. The timing controller of claim 1 , wherein the pulse generator is configured to output the first output pulse at a time that is in synchronization with a start time of a third input pulse of the first enable signal, output the second output pulse after outputting the first output pulse, output the third output pulse after outputting the second output pulse, and a sum of a period of the first output pulse, a period of the second output pulse, and a period of the third output pulse corresponds to a period of the third input pulse, wherein the third input pulse is provided to the count control circuit after the first input pulse is provided to the count control circuit.

3. The timing controller of claim 1 , wherein the first input pulse and each of the second input pulses includes an effective period of image data and a blank period of the image data.

4. The timing controller of claim 3 , wherein the blank period of one of the second input pulses having the identified one period is smaller than the blank period of the first input pulse.

5. The timing controller of claim 1 , wherein the count control circuit comprises:
a counter configured to receive a first reference clock, count a period of the first input pulse to generate the first period, and count a period of the second input pulses to generate the second periods, based on a number of periods of the first reference clock; and
a memory configured to store the first period and the second periods, and output only the second periods.

6. The timing controller of claim 5 , wherein the memory comprises a first-in-first-out memory.

7. The timing controller of claim 5 , wherein the pulse width detector comprises:
a first comparator-selector configured to select a period that is smallest among the second periods;
a second comparator-selector configured to output the selected period upon determining that the selected period is smaller than the first period; and
a divider configured to detect a second reference dock corresponding to one of the second input pulses having the output selected period, and frequency-divides the detected second reference dock by ⅓ to output a divided reference clock.

8. The timing controller of claim 3 , wherein the image data comprises red data, green data, and blue data, and the first output pulse comprises an effective period of the red data and a blank period of the red data, the second output pulse comprises an effective period of the green data and a blank period of the green data, and the third output pulse comprises an effective period of the blue data and a blank period of the blue data.

9. The timing controller of claim 1 , wherein the first input pulse is immediately consecutive to the second input pulses, wherein the second input pulses are immediately consecutive pulses, and wherein the first output pulse, the second output pulse, and the third output pulse are immediately consecutive pulses.

10. The timing controller of claim 1 , wherein the timing controller receives image data, each of the output pulses includes an effective period of the image data and a blank period of the image data, the timing controller applies the image data to a data driver providing data signals to a display panel during the effective period and does not apply the image data to the data driver during the blank period.

Assignees

• Samsung Display Co Ltd

Inventors

• Ahn Ik-Hyun
• Park Jae-Hyoung

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G3/2096 Primary

  Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167) · CPC title

• G09G2310/0232

  Special driving of display border areas · CPC title