Topological qubit fusion

Patent metadata

Field	Value
Publication number	US-10679138-B2
Application number	US-201715632109-A
Country	US
Kind code	B2
Filing date	Jun 23, 2017
Priority date	Feb 5, 2013
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A fusion outcome quasiparticle may be trapped in a potential well of a topological segment. The fusion outcome quasiparticle may be the product of fusion of a first quasiparticle and a second quasiparticle, where the first and the second quasiparticles are localized at ends of a topological segment. The potential well having the fusion outcome quasiparticle trapped therein and a third quasiparticle may be moved relative to each other such that the potential well and the third quasiparticle are brought toward each other. The quasiparticles may be Majorana modes of a nanowire.

First claim

What is claimed is:

1. A quantum computing device, comprising:
at least one nanowire with at least a first topological wire segment defining non-Abelian quasiparticles associated with a first qubit and a second topological wire segment defining non-Abelian quasiparticles associated with a second qubit; and
at least one gate configured to:
selectively induce changes of phase, from topological to nontopological and vice-versa, in the at least one nanowire and induce a potential well in the nanowire that traps a non-Abelian fusion quasiparticle produced by fusing first non-Abelian quasiparticles associated with the first qubit and the second qubit; and
fuse the trapped non-Abelian fusion quasiparticle with a second non-Abelian quasiparticle associated with either the first qubit or the second qubit to produce a non-Abelian fusion outcome quasiparticle associated with a qubit produced by the fusing.

2. The quantum computing device of claim 1 , wherein the at least one nanowire comprises a Majorana wire.

3. The quantum computing device of claim 1 , wherein the at least one gate is configured to cause relative motion of the potential well such that the potential well and the second end of the first topological wire segment are brought towards each other.

4. The quantum computing device of claim 1 , wherein at least one gate is further configured to cause the potential well to brought towards the first topological wire segment.

5. The quantum computing device of claim 1 , further comprising:
a measurement device for measuring the non-Abelian fusion outcome quasiparticle.

6. The quantum computing device of claim 1 , wherein the first qubit comprises first and second non-Abelian quasiparticles, and the second qubit comprises third, fourth, and fifth non-Abelian quasiparticles.

7. The quantum computing device of claim 1 , wherein the at least one nanowire includes a nontopological segment situated between topological segments associated with the first qubit and the second qubit.

8. The quantum computing device of claim 1 , wherein the first qubit is associated with a first encoding and the second qubit is associated with a second encoding, and the fusion quasiparticle has a quasiparticle encoding based on the first encoding and the second encoding.

9. The quantum computing device of claim 8 , the encoding of the first qubit or the second qubit is selected so that the produced qubit corresponds to application of a phase gate on a computational qubit.

10. The quantum computing device of claim 8 , wherein the first encoding corresponds to a state |Ψ A =α 0 |0 +α 1 |1 of the first qubit and the second encoding corresponds to a state |Ψ B )=β 0 |0 +β 1 |1 of the second qubit and the encoding based on the first encoding and the second encoding and produced by fusion is associated with a state |Ψ which is one of:

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Assignees

• Microsoft Technology Licensing Llc

Inventors

• Freedman Michael H
• Wang Zhenghan
• Lutchyn Roman M
• Nayak Chetan
• Bonderson Parsa

Classifications

• G06N10/00 Primary

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H01L39/228

  Electricity · mapped topic

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H04W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title