Space exploration with Bayesian inference

Patent metadata

Field	Value
Publication number	US-10678971-B2
Application number	US-201816040834-A
Country	US
Kind code	B2
Filing date	Jul 20, 2018
Priority date	Jul 20, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A system, a computer program product, and method for physically fabricating an electronic circuit using design space exploration as part of a design process is described. The method begins with defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters. Next an output target to be optimized is defined. A series of one or more test mask shapes are generated to appear on a photo mask using the plurality of design space parameters. A simulation of a post lithography or etch on the series of one or more test mask shapes is performed to produce simulation output values. Next, the simulation output values and corresponding design space parameters are fed into to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate.

First claim

What is claimed is:

1. A method for physically fabricating an electronic circuit using design space exploration as part of a design process, the method comprising:
a) defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters;
b) selecting polygon options as an initial set of shape that are drawn to match post-etch shapes that appear on a wafer;
c) generating a series of one or more test mask shapes to appear on a photo mask using the plurality of design space parameters and the selected polygon options;
d) simulating at least one of a post lithography or etch on the series of one or more test mask shapes to produce simulation output values;
e) feeding the simulation output values and corresponding design space parameters to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate;
repeating steps c through e until a maximum or a minimum output is achieved due to the Bayesian inference algorithm duplicating combinations of design space parameters to investigate or not finding a new maximum or minimum output with any other combinations of design space parameters; and
performing physical design synthesis with a computer to physically implement at least one electronic circuit based on the series of one or more test mask shapes using the next combination of design space parameters.

2. The method of claim 1 , wherein the generating the series of one or more test mask shapes using the plurality of design space parameters includes polygon options drawn exactly to post-etch shapes that appear on a wafer, followed by retargeting which takes into account an etch process, and optical proximity correction to compensate for image errors due to diffraction or process effects during lithography and to transform the series of one or more test mask shapes, which are post-lithographic target shapes, into a photo-mask.

3. The method of claim 1 , wherein the generating the series of one or more test mask shapes using the plurality of design space parameters includes polygon options to target a post-lithographic target shape on wafer, followed by optical proximity correction to compensate for image errors due to diffraction or process effects during lithography and to transform the series of one or more test mask shapes, which are post-lithographic target shapes, into a photo-mask.

4. The method of claim 1 , wherein the generating the series of one or more test mask shapes using the plurality of design space parameters includes polygon options directly to a photo-mask shape.

5. The method of claim 1 , wherein the repeating steps c through e until the maximum or the minimum output is achieved due to the combinations of design space parameters to investigate converge to a single combination.

6. The method of claim 1 , wherein the repeating steps c through e until the maximum or the minimum output is achieved due to the combination of design space parameters to investigate is less than all possible combinations of the design space parameters.

7. A system for physically fabricating an electronic circuit using design space exploration as part of a design process, the system comprising:
a memory;
a processor communicatively coupled to the memory, where the processor is configured to perform
a) defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters;
b) selecting polygon options as an initial set of shape that are drawn to match post-etch shapes that appear on a wafer;
c) generating a series of one or more test mask shapes to appear on a photo mask using the plurality of design space parameters and the selected polygon options;
d) simulating at least one of a post lithography or etch on the series of one or more test mask shapes to produce simulation output values;
e) feeding the simulation output values and corresponding design space parameters to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate;
repeating steps c through e until a maximum or a minimum output is achieved due to the Bayesian inference algorithm duplicating combinations of design space parameters to investigate or not finding a new maximum or minimum output with any other combinations of design space parameters; and
performing physical design synthesis with a computer to physically implement at least one electronic circuit based on the series of one or more test mask shapes using the next combination of design space parameters.

8. The system of claim 7 , wherein the generating the series of one or more test mask shapes using the plurality of design space parameters includes polygon options drawn exactly to post-etch shapes that appear on a wafer, followed by retargeting which takes into account an etch process, and optical proximity correction to compensate for image errors due to diffraction or process effects during lithography and to transform the series of one or more test mask shapes, which are post-lithographic target shapes, into a photo-mask.

9. The system of claim 7 , wherein the generating the series of one or more test mask shapes using the plurality of design space parameters includes polygon options to target a post-lithographic target shape on wafer, followed by optical proximity correction to compensate for image errors due to diffraction or process effects during lithography and to transform the series of one or more test mask shapes, which are post-lithographic target shapes, into a photo-mask.

10. The system of claim 7 , wherein the generating the series of one or more test mask shapes using the plurality of design space parameters includes polygon options directly to a photo-mask shape.

11. The system of claim 7 , wherein the repeating steps c through e until the maximum or the minimum output is achieved due to the combinations of design space parameters to investigate converge to a single combination.

12. The system of claim 7 , wherein the repeating steps c through e until the maximum or the minimum output is achieved due to the combination of design space parameters to investigate is less than all possible combinations of the design space parameters.

13. A computer program product for physically fabricating an electronic circuit using design space exploration as part of a design process, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to:
a) defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters;
b) selecting a polygon option as an initial set of shape that are drawn to match post-etch shapes that appear on a wafer;
c) generating a series of one or more test mask shapes to appear on a photo mask using the plurality of design space parameters and the selected polygon option;
d) simulating at least one of a post lithography or etch on the series of one or more test mask shapes to produce simulation output values;
e) feeding the simulation output values and corresponding design space parameters to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate;
repeating steps c through e until a maximum or a minimum output is achieved due to the Bayesian inference algorithm duplicating combinations of design space parameters to investigate or not finding a new maximum or minimum out

Assignees

• IBM

Inventors

• Sha Jing
• Shao Dongbing
• Dunn Derren

Classifications

• G06N7/005

  Physics · mapped topic

• G06F2111/08

  Probabilistic or stochastic CAD · CPC title

• G03F7/70441

  Optical proximity correction [OPC] · CPC title

• G03F7/705

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title