Data processing device and method for cryptographic processing of data

Patent metadata

Field	Value
Publication number	US-10678707-B2
Application number	US-201715792817-A
Country	US
Kind code	B2
Filing date	Oct 25, 2017
Priority date	Oct 27, 2016
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

According to an embodiment, a data processing device is described comprising a deformer configured to deform a first data block in accordance with a first seed, a seed generator configured to generate a sequence of second seeds, wherein the sequence of second seeds comprises the first seed, a cryptographic processor configured to receive the deformed first data block and, for each second seed, to deform the deformed first data block in accordance with the second seed, to generate a sequence of second data blocks and to cryptographically process each second data block of the sequence of second data blocks to generate a sequence of processed data blocks and an extractor configured to extract a result of the cryptographic processing of the first data block from the sequence of processed data blocks.

First claim

What is claimed is:

1. A data processing device comprising:
a deformer configured to deform a first data block in accordance with a first seed;
a seed generator configured to generate a sequence of second seeds, wherein at least one seed of the sequence of second seeds is the first seed;
a cryptographic processor configured to receive the deformed first data block and, for each second seed, to deform the deformed first data block in accordance with the second seed, to generate a sequence of second data blocks that comprise the first data block and dummy data for the cryptographic procedure, and to process each second data block of the sequence of second data blocks according to the cryptographic processing to generate a sequence of processed data blocks; and
an extractor configured to extract a result of the cryptographic processing of the first data block from the sequence of processed data blocks;
further comprising a fault detector configured to detect a fault based on the sequence of processed data blocks;
wherein the seed generator is configured to generate a plurality of sequences of second seeds, wherein each of the plurality of sequences of second seeds comprises the first seed;
wherein the deformer is configured to deform, for each sequence of second seeds, the first data block in accordance with a first seed;
wherein the cryptographic processor is configured to, for each sequence of second seeds, receive the deformed first data block and, for each sequence of second seeds and for each second seed of the sequence of second seeds, to deform the deformed first data block in accordance with the second seed, to generate, for each sequence of second seeds, a sequence of second data blocks and to cryptographically process each second data block of the sequence of second data blocks to generate a sequence of processed data blocks; and
wherein the fault detector is configured to detect a fault based on a comparison of the sequence of processed data blocks generated for the sequences of second seeds.

2. The data processing device of claim 1 , wherein the deforming of the first data block in accordance with the first seed comprises at least partially XOR-combining the first data block with random numbers generated based on the first seed.

3. The data processing device of claim 1 , wherein the deforming of the deformed first data block in accordance with the first seed comprises at least partially XOR-combining the first data block with random numbers generated based on the first seed.

4. The data processing device of claim 1 , wherein the deforming of the first data block comprises leaving at least one non-secret part of the first data block undeformed.

5. The data processing device of claim 1 , wherein the cryptographic processor is configured to execute a sequence of instructions, each instruction comprising a seed of the sequence of second seeds and instructing the cryptographic processor to cryptographically process the deformed first data block after deforming it in accordance with the seed.

6. The data processing device of claim 1 , wherein the data to be cryptographically processed includes at least one of useful data and key data.

7. The data processing device of claim 1 , wherein the first data block includes both useful data and key data and cryptographically processing the first data block comprises cryptographically processing the useful data in accordance with a key given by the key data.

8. The data processing device of claim 1 , wherein the cryptographic processing includes at least one of encryption, decryption, and hash calculation.

9. The data processing device of claim 1 , further comprising a combiner configured to at least partially combine the sequence of processed data blocks and a memory configured to store the combined sequence of processed data blocks.

10. The data processing device of claim 9 , wherein the combining is an XOR combination.

11. The data processing device of claim 1 , wherein the fault detector is configured to detect a fault based on a comparison of processing results which are equal in case of no fault.

12. The data processing device of claim 1 , wherein the fault detector is configured to detect a fault based on a comparison of a processing result with a known processing answer.

13. The data processing device of claim 1 , wherein the first seeds are different for the sequences of second seeds.

14. The data processing device of claim 1 , wherein the first seeds are the same for at least some of the sequences of second seeds.

15. The data processing device of claim 1 , wherein the sequences of second seeds at least differ in the order of second seeds.

16. The data processing device of claim 1 , further comprising a combiner configured to at least partially combine, for each sequence of second seeds, the sequence of processed data blocks, wherein the fault detector is configured to detect a fault based on a comparison of the combined sequences of processed data blocks generated for the sequences of second seeds.

17. The data processing device of claim 16 , wherein the combiner is configured to, for each sequence of second seeds, generate a plurality of different combinations of the processed data blocks of the sequence of processed data blocks, and the fault detector is configured to detect a fault based on a comparison of combinations generated for the sequences of second seeds which are equal in case of no fault.

18. The data processing device of claim 16 , wherein the combining is an XOR combination.

19. The data processing device of claim 1 , wherein the deformer and the cryptographic processor comprise random number generators configured to generate random numbers based on the seeds.

20. The data processing device of claim 1 , wherein the deformer and the cryptographic processor are implemented by different hardware circuits coupled via an interface, wherein the deformer is configured to provide the deformed masked data to the cryptographic processor via the interface.

21. A method for cryptographic processing of data comprising:
deforming a first data block in accordance with a first seed;
for each second seed, deforming the deformed first data block in accordance with the second seed to generate a sequence of second data blocks that comprise the first data block and dummy data for the cryptographic procedure;
processing each second data block of the sequence of second data blocks according to the cryptographic processing to generate a sequence of processed data blocks;
extracting a result of the cryptographic processing of the first data block from the sequence of processed data blocks;
detecting a fault based on the sequence of processed data blocks;
generating a plurality of sequences of second seeds, wherein each of the plurality of sequences of second seeds comprises the first seed;
deforming, for each sequence of second seeds, the first data block in accordance with a first seed;
receiving, for each sequence of second seeds, the deformed first data block and, deforming, for each sequence of second seeds and for each second seed of the sequence of second seeds, the deformed first data block in accordance with the second seed, to generate, for each sequence of second seeds, a sequence of second data blocks and to cryptographically process each second data block of the sequence of second data blocks to generate a sequence of processed data blocks; and
detecting a fault based on a comparison of the sequence of processed data blocks generated

Assignees

• Infineon Technologies Ag

Inventors

• Poeppelmann Thomas
• Hackenberg Stefan
• Heiss Stefan
• Rau Markus
• Wassmann Stephan

Classifications

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F21/755 Primary

  with measures against power attack · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• H04L9/0662

  with particular pseudorandom sequence generator · CPC title