Techniques for detecting and correcting errors in data

Patent metadata

Field	Value
Publication number	US-10678636-B2
Application number	US-201815908205-A
Country	US
Kind code	B2
Filing date	Feb 28, 2018
Priority date	Feb 28, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Various embodiments are generally directed to techniques for managing errors in data, such as with error-correcting code (ECC), for instance. Some embodiments are particularly directed to providing one or more of error detection, location, and correction for a set of storage memory devices with a management memory device. In one or more embodiments, each of the storage and management memory devices may include a memory chip, such as one of a set of memory chips included in a dual in-line memory module (DIMM). For instance, each memory device be a dynamic random-access memory (DRAM) integrated circuit included in a DIMM. In various embodiments, the set of storage management memory devices may be used to store a memory line, such as an evicted cache line. In many embodiments, cryptographically secure memory encryption and/or integrity may also be provided for the set of storage memory devices with the management memory device.

First claim

The invention claimed is:

1. An apparatus, comprising:
memory comprising instructions; and
circuitry coupled to the memory and arranged to execute the instructions, which cause the circuitry to:
retrieve a set of encoded data blocks associated with a memory line from a set of storage memory devices, the set of encoded data blocks including one encoded data block for each storage memory device in the set of storage memory devices,
retrieve an encoded block correction from a management memory device associated with the set of storage memory devices,
determine a set of decoded data blocks from the set of encoded data blocks,
determine a decoded block correction from the encoded block correction,
combine the set of decoded data blocks into a validation block correction at least in part via an exclusive or (XOR) operator, and
compare the decoded block correction and the validation block correction to identify one or more bit errors in the memory line when the decoded block correction and the validation block correction are different.

2. The apparatus of claim 1 , wherein the set of encoded data blocks and corresponding decoded data blocks comprise a first encoded data block and corresponding decoded data block and a first encoded block correction and corresponding decoded block correction associated with a first storage memory device in the set of storage memory devices and a second encoded block correction and corresponding decoded data block and a second encoded block correction and corresponding decoded block correction associated with a second storage memory device in the set of storage memory devices, and the circuitry in executing the instructions caused to:
combine the first decoded data block and the first decoded block correction to generate a replacement value for the second decoded data block at least in part via the XOR operator;
encode the replacement value for the second decoded data block; and
determine an entropy between the encoded second data block and the encoded replacement value for the second decoded data block to identify when the second storage memory device is a source of at least one of the one or more bit errors.

3. The apparatus of claim 2 , the circuitry in executing the instructions caused to determine the entropy based on a number of bit values that differ between the second encoded data block and the encoded replacement value for the second data block.

4. The apparatus of claim 2 , the circuitry in executing the instructions caused to determine the entropy based on a pattern or clustering in bit values that differ between the second encoded data block and the encoded replacement value for the second decoded data block.

5. The apparatus of claim 2 , the circuitry in executing the instructions caused to replace the second encoded data block with the encoded replacement value for the second encoded data block in the second memory device when the second storage memory device is the source of at least one of the one or more bit errors.

6. The apparatus of claim 2 , the circuitry in executing the instructions caused to:
combine the second decoded data block and the decoded block correction to generate a respective replacement value for the first decoded data block when the second storage memory device is not identified as the source of at least one of the one or more bit errors;
encode the respective replacement value for the first decoded data block; and
determine an entropy between the first encoded data block and the encoded respective replacement value for the first data block to identify when the first storage memory device is a source of at least one of the one or more bit errors.

7. The apparatus of claim 1 , wherein the set of encoded block correction and corresponding decoded data blocks comprises a first encoded block correction and corresponding decoded data block and a first encoded/decoded block correction associated with a first storage memory device in the set of storage memory devices and a second encoded block correction and corresponding decoded data block and a second encoded block correction and corresponding decoded block correction associated with a second storage memory device in the set of storage memory devices, and the circuitry in executing the instructions caused to:
flip a first bit in the first encoded data block to produce a first encoded test value;
determine a first decoded test value based on the first encoded test value;
combine the first decoded test value with the first decoded block correction generate a replacement value for the second decoded data block at least in part via the XOR operator;
encode the replacement value for the second decoded data block; and
determine an entropy between the encoded second data block and the encoded replacement value for the second decoded data block to identify when a combination of the first and second storage memory devices are a source of at least one of the one or more bit errors.

8. The apparatus of claim 1 , wherein the set of encoded block correction and corresponding decoded data blocks comprises a first encoded block correction and corresponding decoded data block associated with a first storage memory device in the set of storage memory devices and a second encoded/decoded data block associated with a second storage memory device in the set of storage memory devices, and the circuitry in executing the instructions caused to:
combine the first decoded data block and the second decoded data block to generate a replacement value for the decoded block correction at least in part via the XOR operator;
encode the replacement value for the second decoded data block; and
determine an entropy between the encoded block correction and the encoded replacement value for the block correction to identify the management memory device as a source of at least one of the one or more bit errors.

9. The apparatus of claim 1 , the circuitry in executing the instructions caused to utilize a decryption algorithm to determine the set of decoded data blocks comprising the memory line from the set of encoded data blocks and the decoded block correction from the encoded block correction.

10. The apparatus of claim 9 , the decryption algorithm comprising a block cipher with an input size equal to a bit size of individual encoded data blocks in the set of data blocks.

11. The apparatus of claim 10 , the decryption algorithm to decode a respective encoded data block based on an address of the respective encoded data block.

12. The apparatus of claim 10 , the decryption algorithm to decode a respective encoded data block based on a key.

13. The apparatus of claim 12 , the circuitry in executing the instructions caused to identify the key based on metadata or address bits.

14. The apparatus of claim 1 , comprising the set of storage memory devices and the management memory device and wherein the set of storage memory devices and the management memory device include a common type of memory device.

15. The apparatus of claim 1 , wherein each data block in the set of data blocks comprises a row of the memory line.

16. A method, comprising:
retrieving a set of encoded data blocks associated with a memory line from a set of storage memory devices in a memory module and an encoded block correction from a management memory device in the memory module, the set of encoded data blocks including one encoded data block for each storage memory device in the set of storage memory devices;
determining a set of decoded data blocks comprising the memory line from the set of encoded data blocks and a decoded block correct

Assignees

• Intel Corp

Inventors

• Durham David M

Classifications

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L9/0618

  Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• H04L2209/34

  Encoding or coding, e.g. Huffman coding or error correction · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title