Display driver circuit for adjusting framerate to reduce power consumption

Patent metadata

Field	Value
Publication number	US-10674112-B2
Application number	US-201916415100-A
Country	US
Kind code	B2
Filing date	May 17, 2019
Priority date	Sep 18, 2018
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

A display driver circuit includes a source driver configured to output display data to data lines, a controller configured to control the source driver, based on a synchronization signal, and a frequency adjusting circuit configured to extend a first time interval of the synchronization signal from a first length to a second length, such that time interval in which the display data is not output to the data lines is extended, when second image data are not received from an external device during a reference time interval after first image data are received from the external device, and shorten the first time interval, from the second length to a third length, when an instruction is received from the external device after the first time interval is extended to the second length.

First claim

What is claimed is:

1. A display driver circuit comprising:
a source driver configured to output display data to data lines;
a controller configured to control the source driver, based on a synchronization signal; and
a frequency adjusting circuit configured to:
extend a first time interval of the synchronization signal from a first length to a second length, such that time interval in which the display data is not output to the data lines is extended, when second image data are not received from an external device during a reference time interval after first image data are received from the external device; and
shorten the first time interval, from the second length to a third length, when an instruction is received from the external device after the first time interval is extended to the second length.

2. The display driver circuit of claim 1 , wherein the frequency adjusting circuit is further configured to:
output the synchronization signal at a second time interval after the first time interval; and
maintain the second time interval such that time interval at which the display data is output to the data lines is maintained.

3. The display driver circuit of claim 1 , wherein the frequency adjusting circuit is further configured to shorten the first time interval of the synchronization signal, from the second length to the third length, before the second image data are received based on the instruction.

4. The display driver circuit of claim 1 , wherein the third length is identical to the first length.

5. The display driver circuit of claim 1 , wherein the frequency adjusting circuit is further configured to receive the instruction, and wherein the instruction is generated based on touch event of a touch panel.

6. The display driver circuit of claim 1 , wherein the frequency adjusting circuit is further configured to shorten the first time interval from the second length to the third length based on the instruction before the second image data are received from the external device.

7. The display driver circuit of claim 6 , wherein the frequency adjusting circuit is further configured to:
extend the first time interval from the first length to the second length by a first fixed length; and
shorten the first time interval from the second length to the third length by a second fixed length.

8. A display driver circuit comprising:
a source driver configured to output display data to data lines connected to pixels;
a controller configured to control the source driver, based on a synchronization signal;
a power controller configured to turn off the source driver during a first time interval, based on the synchronization signal; and
a frequency adjusting circuit configured to:
increase a period of the synchronization signal, from a first value to a second value, such that the first time interval is extended, when second image data are not received from an external device during a reference time interval after first image data are received from the external device; and
reduce the period of the synchronization signal, from the second value to a third value, when the second image data are received from the external device.

9. The display driver circuit of claim 8 , wherein, when the source driver is turned off, a power that is supplied to the source driver is shut off.

10. The display driver circuit of claim 8 , wherein the power controller is further configured to turn on the source driver during a second time interval, based on the synchronization signal.

11. The display driver circuit of claim 10 , wherein the source driver is further configured to not output the display data in the first time interval and output the display data in the second time interval.

12. The display driver circuit of claim 8 , further comprising a scan driver configured to drive scan lines connected to the pixels,
wherein the power controller is further configured to turn off the scan driver during the first time interval, based on the synchronization signal.

13. The display driver circuit of claim 8 , wherein the frequency adjusting circuit is further configured to generate an emission signal such that a period of emission of a light from each of the pixels is maintained regardless of the period of the synchronization signal.

14. The display driver circuit of claim 13 , wherein the period of the emission is associated with a quality of an image that is displayed in a display panel, based on the display data.

15. A display driver circuit comprising:
a source driver configured to output display data to data lines;
a controller configured to control the source driver, based on a synchronization signal; and
a frequency adjusting circuit configured to:
lower a frequency of the synchronization signal, from a first value to a second value, when second image data are not received from an external device during a reference time interval after first image data are received from the external device;
increase the frequency of the synchronization signal, from the second value to a third value, when the second image data are received from the external device; and
adjust the frequency of the synchronization signal, such that time interval in which the display data are output is maintained.

16. The display driver circuit of claim 15 , wherein the frequency adjusting circuit is further configured to lower the frequency of the synchronization signal, such that time interval in which the display data are not output is extended.

17. The display driver circuit of claim 15 , wherein the frequency adjusting circuit comprises:
a counter configured to count the time interval that the second image data are not received after the first image data are received from the external device;
a comparator configured to compare the time interval with the reference time interval; and
a frequency controller configured to adjust the frequency of the synchronization signal, based on a comparison result in the comparator.

18. The display driver circuit of claim 15 , wherein the third value is identical to the first value.

19. The display driver circuit of claim 15 , wherein the frequency adjusting circuit is further configured to output a touch signal to a touch circuit at a frequency higher than the second value.

20. The display driver circuit of claim 19 , wherein the frequency adjusting circuit is further configured to increase the frequency of the synchronization signal, from the second value to the third value, when a instruction received from the touch circuit, and
wherein the instruction is generated based on touch event of a touch panel.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Young-Bae
• Park Junho
• Lee Sang-Min
• Cheon Seongmin
• Kwon Kyoung Hwan

Classifications

• G06F1/3265

  Power saving in display device · CPC title

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title

• G06F3/047

  using sets of wires, e.g. crossed wires · CPC title

• H04N7/0127 Primary

  by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter · CPC title

• H04N7/56

  Synchronising systems therefor · CPC title