Multilayer ceramic capacitor and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10672559-B2
Application number	US-201816044834-A
Country	US
Kind code	B2
Filing date	Jul 25, 2018
Priority date	Jul 26, 2017
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

A multilayer ceramic capacitor includes: a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers are alternately stacked, the plurality of internal electrode layers being alternately exposed to a first edge face and a second edge face of the multilayer structure, wherein 1.5≤Db/Da≤10.0 is satisfied in a side margin region that covers edge portions to which the plurality of internal electrode layers extend toward two side faces other than the first edge face and the second edge face, when Da is an average grain diameter of a main component ceramic within 20 μm from an edge of the plurality of internal electrode layers in the side margin region and Db is an average grain diameter of a main component ceramic within 20 μm from a surface layer of the side margin region.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers are alternately stacked, a main component of the plurality of dielectric layers being ceramic, the multilayer structure having a rectangular parallelepiped shape, the plurality of internal electrode layers being alternately exposed to a first edge face and a second edge face of the multilayer structure, the first edge face facing with the second edge face,
wherein
1.5≤Db/Da≤10.0 is satisfied in a side margin region that covers edge portions to which the plurality of internal electrode layers extend toward two side faces of the multilayer structure other than the first edge face and the second edge face, when Da is an average grain diameter of a main component ceramic within 20 μm from an edge of the plurality of internal electrode layers in the side margin region in an extending direction of the plurality of internal electrode layers which extend, respectively, toward the side margin region and Db is an average grain diameter of a main component ceramic within 20 μm from a surface layer of the side margin region in the extending direction.

2. The multilayer ceramic capacitor as claimed in claim 1 , wherein the main component ceramic of the side margin region is barium titanate.

3. The multilayer ceramic capacitor as claimed in claim 2 ,
wherein the side margin region includes Mn and/or Mg, and
wherein a total concentration of Mn and Mg in the side margin region is 0.3 atm % or less.

4. The multilayer ceramic capacitor as claimed in claim 1 , wherein:
the average grain diameter Da is closer to an average grain diameter of a main component ceramic of a capacity region than the average grain diameter Db is; and
the capacity region is a region in which a set of internal electrode layers exposed to the first edge face of the multilayer structure face with another set of internal electrode layers exposed to the second edge face of the multilayer structure.

5. A manufacturing method of a multilayer ceramic capacitor comprising:
a first step of providing a pattern of a metal conductive paste on a green sheet including main component ceramic grains;
a second step of obtaining a ceramic multilayer structure by stacking a plurality of lamination units obtained by the first step so that positions of the pattern are alternately shifted; and
a third step of baking the ceramic multilayer structure and obtaining a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers are alternately stacked, the multilayer structure having a rectangular parallelepiped shape, the plurality of internal electrode layers being alternately exposed to a first edge face and a second edge face of the multilayer structure, the first edge face facing with the second edge face,
wherein:
in the third step, grain growth of a surface region of a side margin region is promoted more than grain growth of an inner region of the side margin region and thereby 1.5≤Db/Da≤10.0 is satisfied in the side margin region when Da is an average grain diameter of a main component ceramic within 20 μm from an edge of the plurality of internal electrode layers in the side margin region in an extending direction of the plurality of internal electrode layers which extend, respectively, toward the side margin region and Db is an average grain diameter of the main component ceramic within 20 μm from a surface layer of the side margin region in the extending direction; and
the side margin region is a region that covers edge portions to which the plurality of internal electrode layers extend toward two side faces of the multiple structure other than the first edge face and the second edge face.

Assignees

• Taiyo Yuden Kk

Inventors

• Inomata Yasuyuki
• Kono Yasuhisa
• Amano Mina

Classifications

• H01G4/1227 Primary

  based on alkaline earth titanates · CPC title

• H01G4/308

  made by transfer techniques · CPC title

• H01G4/224

  Housing; Encapsulation · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title