Chips including classical and quantum computing processors

Patent metadata

Field	Value
Publication number	US-10671559-B2
Application number	US-201515127695-A
Country	US
Kind code	B2
Filing date	Mar 23, 2015
Priority date	Mar 21, 2014
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

An apparatus includes a substrate, a classical computing processor formed on the substrate, a quantum computing processor formed on the substrate, and one or more coupling components between the classical computing processor and the quantum computing processor, the one or more coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor.

First claim

What is claimed is:

1. An apparatus comprising: a substrate;
a classical computing processor formed on the substrate;
a quantum computing processor formed on the substrate; and
one or more interprocessor coupling components between the classical computing processor and the quantum computing processor, the one or more interprocessor coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor, wherein the classical computing processor comprises a plurality of reciprocal quantum logic gates arranged to provide at least one of a digital signal processor and a serial microprocessor, and wherein the one or more interprocessor coupling components comprise an inductive coupler,
wherein the classical computing processor comprises a plurality of classical unit cells, each classical unit cell comprising a plurality of active components, wherein each active component is configured to generate a classical bit,
wherein the quantum computing processor comprises a plurality of quantum unit cells, each quantum unit cell comprising a plurality of qubits,
wherein, for each classical unit cell, a first subset of the plurality of active components is coupled, by interprocessor coupling components, to a respective first subset of qubits within a corresponding quantum unit cell,
wherein, for each classical unit cell, a second subset of the plurality of active components is coupled to the first subset of active components, and
wherein, for each quantum unit cell, a second subset of the plurality of qubits is coupled to the first subset of qubits.

2. The apparatus of claim 1 , wherein the quantum computing processor is configured to receive output data from the classical computing processor and use the received output data as input data for a quantum computation to be carried out by the quantum computing processor.

3. The apparatus of claim 2 , wherein the quantum computing processor is configured to be programmed using the output data.

4. The apparatus of claim 1 , wherein the one or more interprocessor coupling components connect an output of the classical computing processor to an input of the quantum computing processor.

5. The apparatus of claim 1 , wherein the one or more interprocessor coupling components connect an output of the quantum computing processor to an input of the classical computing processor.

6. The apparatus of claim 1 , wherein each of the quantum computing processor and the classical computing processor comprises a superconducting quantum interference device (SQUID).

7. The apparatus of claim 1 , wherein each of the quantum computing processor and the classical computing processor comprises at least one Josephson junction and an inductor.

8. The apparatus of claim 1 , wherein the one or more interprocessor coupling components comprise a superconducting wire.

9. The apparatus of claim 1 , wherein each of the quantum computing processor and the classical computing processor comprises electronic components comprising a superconducting material.

10. The apparatus of claim 9 , wherein the superconducting material comprises aluminum, niobium or a lead alloy.

11. The apparatus of claim 1 , wherein the one or more interprocessor coupling components comprise an array of superconducting cavity quantum electrodynamics (QED) transmission lines.

12. The apparatus of claim 1 , wherein the classical computing processor formed on the substrate and the quantum computing processor formed on the substrate are part of a single chip.

13. The apparatus of claim 1 , wherein the classical computing processor is configured to perform classical annealing computations and the quantum computing processor is configured to perform quantum annealing computations.

14. The apparatus of claim 1 , further comprising a magnetic component configured to impose a transverse magnetic field on the substrate,
the magnetic component further being configured to impose a transverse magnetic field of time-varying strength while the quantum computing processor is performing a particular operation, and to impose a transverse magnetic field of zero or negligible strength while the classical computing processor is performing a particular operation.

15. The apparatus of claim 1 ,
wherein, for each classical unit cell, the second subset of active components is coupled to a subset of active components of another classical unit cell, and
wherein, for each quantum unit cell, the second subset of qubits is coupled to a subset of qubits of another quantum unit cell.

16. The apparatus of claim 15 , wherein, for each quantum unit cell, the second subset of qubits is coupled to the subset of qubits of another quantum unit cell by a ferromagnetic coupling.

17. The apparatus of claim 1 , wherein the one or more interprocessor coupling components between the classical computing processor and the quantum computing processor comprise a post-processing element,
the post-processing element being configured to do either or both of
(i) receiving data from the quantum computing processor, modifying the data, and sending the modified data to the classical computing processor, and
(ii) receiving data from the classical computing processor, modifying the data, and sending the modified data to the quantum computing processor.

18. The apparatus of claim 1 , wherein each of the one or more interprocessor coupling components is configured to be activated by an application of an external current, and to be deactivated by a withdrawal of an external current.

19. The apparatus of claim 9 , wherein the electronic components of the quantum computing processor and the electronic components of the classical computing processor comprise the same superconducting material.

20. An apparatus comprising: a substrate;
a classical computing processor formed on the substrate;
a quantum computing processor formed on the substrate; and
one or more interprocessor coupling components between the classical computing processor and the quantum computing processor, the one or more interprocessor coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor, wherein the classical computing processor comprises a plurality of reciprocal quantum logic gates arranged to provide at least one of a digital signal processor and a serial microprocessor, and wherein the one or more interprocessor coupling components comprise an inductive coupler; and
a magnetic component configured to impose a transverse magnetic field on the substrate,
the magnetic component further being configured to impose a transverse magnetic field of time-varying strength while the quantum computing processor is performing a particular operation, and to impose a transverse magnetic field of zero or negligible strength while the classical computing processor is performing a particular operation.

21. An apparatus comprising:
a substrate;
a classical computing processor formed on the substrate;
a quantum computing processor formed on the substrate; and
one or more interprocessor coupling components between the classical computing processor and the quantum computing processor, the one or more interprocessor coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor,
wherein the classic

Assignees

• Google Llc

Inventors

• Mohseni Masoud
• Neven Hartmut

Classifications

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H01P5/08

  for linking dissimilar lines or devices (H01P1/16, H01P5/04 take precedence; linking lines of the same kind but with different dimensions H01P5/02) · CPC title

• H01L27/18

  Electricity · mapped topic

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• H01L39/223

  Electricity · mapped topic