System and method for merge assist using vehicular communication
US-2017369067-A1 · Dec 28, 2017 · US
US10671027B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10671027-B2 |
| Application number | US-201816013568-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 20, 2018 |
| Priority date | Jun 20, 2018 |
| Publication date | Jun 2, 2020 |
| Grant date | Jun 2, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
In embodiments, a system may comprise a circuit component to perform a function; and a supervisor component (e.g., a safety component) coupled to the circuit component to monitor proper functioning of the circuit component. The circuit component may be configured to initiate provision of diagnostic information to the supervisor component, or to indicate to the safety component whether the circuit component will be responsive to a query from the safety component for diagnostic information.
Opening claim text (preview).
What is claimed is: 1. An electronic component, comprising: an interface to couple the electronic component to a supervisor component responsible for monitoring the electronic component for proper operation; and logic circuitry coupled to the interface to signal the supervisor component, via the interface, to initiate provision of diagnostic information to the supervisor component, or to indicate to the supervisor component whether the electronic component will be responsive to a query from the supervisor component for diagnostic information; wherein the interface comprises at least three signal lines for asserting or de-asserting at least three corresponding signals, and the logic circuitry is to selectively assert or de-assert the at least three corresponding signals to signal the supervisor component, via the interface, a current state of the electronic component, including de-assertion of the at least three corresponding signals to signal the supervisor component, via the interface, that the electronic component is currently in a power off state, where the electronic component has no power and is not ready to respond to a query from the supervisor component for diagnostic information. 2. The electronic component of claim 1 , wherein the current state of the electronic component is: a power off state where the electronic component has no power, and is not ready to respond to a query from the supervisor component for diagnostic information, a power on state where the electronic component is powering up, but not ready to respond to a query from the supervisor component for diagnostic information, a reset state where the electronic component is powered up, but not ready to respond to a query from the supervisor component for diagnostic information, an OK state where the electronic component is powered up and operational, and ready to respond to a query from the supervisor component for diagnostic information, a not OK (NOK) state where the electronic component is powered up, detected a fatal or unrecoverable error, and may or may not be able to respond to a query from the supervisor component for diagnostic information, or a self-diagnostic state where the electronic component is powered up, performing self-diagnostic, and the supervisor component should not be accessing the electronic component for diagnostic information until self-diagnostic is completed. 3. The electronic component of claim 1 , wherein the logic circuitry is to further respectively transition the at least three corresponding signals from de-assertion to a weak pull up high state to signal the supervisor component, via the interface, that the electronic component is currently in a power on state, where the electronic component is powering up, and not ready to respond to a query from the supervisor component for diagnostic information. 4. The electronic component of claim 1 , wherein the logic circuitry is to respectively transition the at least three corresponding signals to a weak pull up high state to signal the supervisor component, via the interface, that the electronic component is currently in a reset state, where the electronic component is powered up, and not ready to respond to a query from the supervisor component for diagnostic information. 5. The electronic component of claim 1 , wherein the logic circuitry is to assert a first of the at least three corresponding signals, and de-assert a second and a third of the at least three signals to signal the supervisor component, via the interface, that the electronic component is currently in an OK state, where the electronic component is powered up and operational, and ready to respond to a query from the supervisor component for diagnostic information; and wherein the logic circuitry is to further toggle a selected one of the second and third of the at least three signals to indicate to the supervisor component, via the interface, that the electronic component has a message for the supervisor component. 6. The electronic component of claim 1 , wherein the logic circuitry is to de-assert a first of the at least three corresponding signals, assert a second of the at least three signals, and de-assert or transition a third of the at least three signals to a weak pull up high state to signal the supervisor component, via the interface, that the electronic component is currently in a not OK state, where the electronic component is powered up, detected a fatal or unrecoverable error, and may or may not be able to respond to a query from the supervisor component for diagnostic information. 7. The electronic component of claim 1 , wherein the logic circuitry is to assert a first and a second of the at least three corresponding signals, and transition a third of the at least three signals to a weak pull up high state to signal the supervisor component, via the interface, that the electronic component is currently in a self-diagnostic state, where the electronic component is powered up, performing self-diagnostic, and the electronic component is not being accessed by the supervisor component for diagnostic information until self-diagnostic is completed. 8. The electronic component of claim 2 , wherein at least three corresponding signals comprise an OK signal, a NOK signal and an Alert # signal. 9. The electronic component of claim 1 , wherein the interface is a first interface, and the electronic component further comprises a second interface to receive a query from the supervisor component for diagnostic information, the query being forwarded to the logic circuitry to respond, or to send diagnostic information to the supervisor component to respond to a query from the supervisor component for diagnostic information, the diagnostic information sent being provided by the logic circuitry. 10. An electronic component, comprising: an interface to couple the electronic component to a supervisee component to monitor the supervisee component for proper operation; logic circuitry coupled to the interface to receive, via the interface, signals from the supervisee component to initiate provision of diagnostic information to the electronic component, or to indicate to the electronic component that the supervisee component will be responsive to a query from the electronic component for diagnostic information; and a watchdog timer coupled to the logic circuitry, and use by the logic circuitry to ensure the supervisee component has not taken an amount of time in excess of a timing threshold to transition from a self-diagnostic state to an OK state when the supervisee component is performing a key-on self-test. 11. The electronic component of claim 10 , wherein the interface is a first interface, and the electronic component further comprises a second interface to send a query to a supervisee component for diagnostic information, the query being sent on behalf of the logic circuitry, or to receive diagnostic information from the supervisee component in response to the query from the electronic component for diagnostic information, the diagnostic information received being forwarded to the logic circuitry. 12. The electronic component of claim 10 , further comprising a watchdog timer coupled to the logic circuitry, and use by the logic circuitry to ensure the supervisee component has not taken an amount of time in excess of a timing threshold to transition from a power on or a reset state to an OK state. 13. The electronic component of claim 10 , further comprising a watchdog timer coupled to the logic circuitry, and use by the logic circuitry to ensure the supervisee component has not taken an amount of time in excess of a timing threshold to transition from a
Inter-integrated circuit (I2C) · CPC title
on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title
electric · CPC title
electric · CPC title
characterized by the autonomous decision making process, e.g. artificial intelligence, predefined behaviours (using knowledge based models G06N5/00) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.