Detection of disturbances of a power supply

Patent metadata

Field	Value
Publication number	US-10670666-B2
Application number	US-201816047743-A
Country	US
Kind code	B2
Filing date	Jul 27, 2018
Priority date	Oct 27, 2015
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.

First claim

What is claimed is:

1. A detection circuit, comprising:
a current mirror comprising a first transistor and a second transistor, wherein a gate terminal of the first transistor, a drain terminal of the first transistor, and a gate terminal of the second transistor are coupled as a first node, wherein a source terminal of the first transistor and a power supply terminal are coupled as a second node, and wherein the power supply terminal is configured to receive a first power supply voltage;
a first current source comprising a first terminal and a second terminal, wherein the first terminal of the first current source is coupled to the drain terminal of the first transistor, and wherein the second terminal of the first current source is coupled to a ground potential;
a second current source coupled between a drain terminal of the second transistor and the ground potential, wherein an output voltage of the detection circuit, drawn from a third node located between the drain terminal of the second transistor and the second current source, is configured to vary in response to a variation of the first power supply voltage at the power supply terminal;
a first resistor coupled between a source terminal of the second transistor and a fourth node;
a second resistor coupled between the fourth node and the second node; and
a first capacitive element coupled between the fourth node and the ground potential.

2. The detection circuit of claim 1 , wherein the second resistor is configured to set a threshold of detection of the variation of the first power supply voltage at the power supply terminal.

3. The detection circuit of claim 2 , wherein a reference current common to the first current source and the second current source is obtained by a ratio of a temperature-independent voltage to a resistance of the second resistor.

4. The detection circuit of claim 3 , wherein the threshold of detection of the variation of the first power supply voltage at the power supply terminal is independent of a temperature variation.

5. The detection circuit of claim 1 , wherein the first transistor and the second transistor comprise MOS transistor s, and wherein a ratio of a width of a gate of the first transistor to a length of the gate of the first transistor is different from a ratio of a width of a gate of the second transistor to a length of the gate of the second transistor.

6. The detection circuit of claim 1 , wherein the first current source and the second current source comprise MOS transistor s, and wherein a ratio of a width of a gate of the first current source to a length of the gate of the first current source is different from a ratio of a width of a gate of the second current source to a length of the gate of the second current source.

7. The detection circuit of claim 1 , wherein the first transistor and the second transistor comprise bipolar transistor s.

8. The detection circuit of claim 1 , wherein the first current source comprises a current transistor.

9. The detection circuit of claim 1 , wherein the second resistor comprises a programmable resistor.

10. The detection circuit of claim 1 , wherein the first power supply voltage comprises a voltage upstream of a voltage regulator configured to generate a second power supply voltage from the first power supply voltage.

11. The detection circuit of claim 1 , wherein the first power supply voltage comprises a voltage downstream of a voltage regulator configured to generate the first power supply voltage from a second power supply voltage.

12. The detection circuit of claim 1 , wherein the detection circuit is configured to detect an unauthorized access to an integrated chip card based on the variation of the first power supply voltage at the power supply terminal.

13. A device, comprising:
a power supply regulator coupled between a terminal of application of a first power supply voltage and a ground potential, wherein the power supply regulator is configured to generate a second power supply voltage from the first power supply voltage;
a main circuit comprising a first terminal coupled to the power supply regulator and configured to receive the second power supply voltage, the main circuit further comprising a second terminal coupled to the ground potential; and
a detection circuit configured to provide the main circuit an indication signal indicative of a disturbance in the first power supply voltage or in the second power supply voltage, the detection circuit comprising:
a current mirror comprising a first transistor and a second transistor, wherein a gate terminal of the first transistor, a drain terminal of the first transistor, and a gate terminal of the second transistor are coupled as a first node, wherein a source terminal of the first transistor and a power supply terminal are coupled as a second node, and wherein the power supply terminal is configured to receive the first power supply voltage or the second power supply voltage;
a first current source comprising a first terminal and a second terminal, wherein the first terminal of the first current source is coupled to the drain terminal of the first transistor, and wherein the second terminal of the first current source is coupled to the ground potential;
a second current source coupled between a drain terminal of the second transistor and the ground potential, wherein an output voltage of the detection circuit, drawn from a third node located between the drain terminal of the second transistor and the second current source, is configured to vary in response to the disturbance in the first power supply voltage or in the second power supply voltage;

a first resistor coupled between a source terminal of the second transistor and a fourth node;
a second resistor coupled between the fourth node and the second node; and
a first capacitive element coupled between the fourth node and the ground potential.

14. The device of claim 13 , wherein the indication signal is generated based on the output voltage of the detection circuit.

15. The device of claim 13 , wherein the main circuit comprises an integrated circuit card.

16. The device of claim 15 , wherein the detection circuit is configured to detect an unauthorized access to an integrated chip card based on the disturbance in the first power supply voltage or in the second power supply voltage.

17. The device of claim 16 , wherein the indication signal is configured to cause the integrated chip card to shut down in response to a detection of the unauthorized access to the integrated chip card.

18. The device of claim 13 , wherein the second resistor is configured to set a threshold of detection of the disturbance in the first power supply voltage or in the second power supply voltage.

19. The device of claim 18 , wherein a reference current common to the first current source and the second current source is obtained by a ratio of a temperature-independent voltage to a resistance of the second resistor.

20. The device of claim 19 , wherein the threshold of detection of the disturbance in the first power supply voltage or in the second power supply voltage is independent of a temperature variation.

21. The device of claim 13 , wherein the first transistor and the second transistor comprise MOS transistor s.

22. The device of claim 21 , wherein a ratio of a width of a gate of the first transistor to a length of the gate of the first transistor is different from a ratio of a width of a gate of the second transistor to a length of t

Assignees

• St Microelectronics Alps Sas

Inventors

• Leduc Bruno
• Bernon Pascal
• Clin Stephane

Classifications

• G01R19/165 Primary

  Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values · CPC title

• G01R15/14

  Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks · CPC title

• G01R3/00

  Apparatus or processes specially adapted for the manufacture {or maintenance} of measuring instruments {, e.g. of probe tips} · CPC title

• G01R31/40 Primary

  Testing power supplies (testing photovoltaic devices H02S50/10) · CPC title