Device, system, and method for determining an address of a component arranged in a structure

Patent metadata

Field	Value
Publication number	US-10667369-B2
Application number	US-201816489451-A
Country	US
Kind code	B2
Filing date	Mar 1, 2018
Priority date	Mar 9, 2017
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A device, system, and method determine addresses of nodes for an arrangement including strings that have nodes and a splitter. The system includes a controller device connected to a first string, the first string also connected to the splitter. The system includes a bus configuration connecting the nodes to one another and to the controller device. The controller device transmits first signals to the nodes of the first string and sequentially receives first responses. The controller device assigns addresses to the nodes of the first string. The controller device generates a second signal that defines a path to a splitter output. The controller device sequentially receives second responses from nodes of a second string on the splitter output and then assigns addresses to the nodes of the second string.

First claim

The invention claimed is:

1. A system for determining addresses of nodes, comprising:
an arrangement including:
a first string including first nodes of the nodes;
a splitter including a plurality of splitter outputs; and
a second string connected to a first one of the splitter outputs, the second string including second nodes of the nodes;
a controller device connected to a first end of the first string, a second end of the first string connected to the splitter; and
a bus configuration configured to connect the nodes to one another and to the controller device, the bus configuration including:
a first line for transmitting signals in a first direction; and
a second line transmitting signals in a second direction,
wherein the controller device is configured to transmit a first signal on the first line that is received by the first nodes,
wherein the controller device is configured to sequentially receive first responses to the first signal on the second line from the first nodes each within a predetermined time period,
wherein each of the first nodes utilizes a first node output to transmit the first signal on the first line after transmitting the respective first response,
wherein the controller device is configured to assign first addresses to the first nodes based on the sequential receiving of the first responses,
wherein the controller device is configured to determine a time out of the first signal when no further response is received within the predetermined time period from the first string,
wherein the controller device is configured to generate a second signal that defines a path to a selected one of the splitter outputs,
wherein the controller device is configured to transmit the second signal on the first line to be received by the splitter,
wherein, when the selected splitter output is the first splitter output, the controller device is configured to sequentially receive second responses to the first signal on the second line from the second nodes each within the predetermined time period, and
wherein the controller device is configured to assign second addresses to the second nodes based on the sequential receiving of the second responses.

2. The system of claim 1 , wherein the controller device is configured to generate a plurality of second signals, a number of the second signals corresponding to a number of the splitter outputs.

3. The system of claim 1 , wherein the first and second responses are generated and transmitted by the first and second nodes, respectively, when each of the first and second nodes receives the first signal for a time duration, the time duration being less than the predetermined time period.

4. A method for determining addresses of nodes in an arrangement, the arrangement including a first string including first nodes of the nodes, a first end of the first string connected to the controller device, a splitter connected to a second end of the first string including a plurality of splitter outputs, and a second string connected to a first one of the splitter outputs, the second string including second nodes of the nodes, the method comprising the steps of:
connecting the nodes to one another and to the controller device via a bus configuration, the connecting step including,
connecting an output to a first line for transmitting signals in a first direction on the bus configuration; and
connecting an input to a second line for receiving signals in a second direction on the bus configuration;
transmitting a first signal on the first line that is received by the first nodes,

sequentially receiving first responses to the first signal on the second line from the first nodes each within a predetermined time period, each of the first nodes utilizing a first node output to transmit the first signal on the first line after transmitting the respective first response,
assigning first addresses to the first nodes based on the sequential receiving of the first responses,
determining a time out of the first signal when no further response is received within the predetermined time period from the first string,
generating a second signal that defines a path to a selected one of the splitter outputs,
transmitting the second signal on the first line to be received by the splitter,
when the selected splitter output is the first splitter output, sequentially receiving second responses to the first signal on the second line from the second nodes each within the predetermined time period, and
assigning second addresses to the second nodes based on the sequential receiving of the second responses.

5. The method of claim 4 , wherein the first signal is asserted on the first line continuously, and wherein the second signal is asserted on the first line with a signal pattern.

6. The method of claim 4 , wherein the controller device generates a plurality of second signals, a number of the second signals corresponding to a number of the splitter outputs.

7. The method of claim 4 , wherein the plurality of splitter outputs is two outputs.

8. The method of claim 7 , further including the step of determining a second time out of the first signal when no further response is received within the predetermined time period from the second string.

9. The method of claim 7 , further including the step of determining a third time out of the first signal when no further response is received within the predetermined time period from a second splitter output of the splitter outputs.

10. The method of claim 8 , wherein the arrangement includes a plurality of branches, and assigning addresses of each of the first and second nodes in the plurality of branches when the first or second time out is determined.

11. The method of claim 10 , further including the step of determining an overall map of the arrangement based on received responses from the nodes.

12. A lighting array including the system for determining addresses of nodes according to claim 1 .

13. The lighting array of claim 12 , wherein the second signal includes at least one segment, and wherein the at least one segment corresponds to a splitter level, and wherein the splitter level corresponds to a number of splitters from the controller device ( 120 ).

14. The lighting array of claim 13 , wherein the splitter level of the splitter is a first splitter level, the second signal including one segment.

15. The lighting array of claim 14 , further comprising:
a further splitter including a plurality of further splitter outputs; and
a third string connected to a first one of the further splitter outputs, the third string including third nodes of the nodes.

Assignees

• Signify Holding Bv

Inventors

• Smola Paul

Classifications

• H05B47/23

  of two or more light sources connected in series · CPC title

• H05B47/16

  by timing means · CPC title

• H05B45/10

  Controlling the intensity of the light · CPC title

• H05B45/20

  Controlling the colour of the light · CPC title

• H05B45/00 Primary

  Circuit arrangements for operating light-emitting diodes [LED] · CPC title