Partitioned delta-sigma modulator for high-speed applications

Patent metadata

Field	Value
Publication number	US-10666286-B1
Application number	US-201916264589-A
Country	US
Kind code	B1
Filing date	Jan 31, 2019
Priority date	Jan 31, 2019
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A partitioned delta-sigma modulator for high-speed applications includes a plurality of modulation stages arranged in parallel to input and output terminals of the modulator and interconnected to one another in series. In some aspects, each of the plurality of modulation stages is configured to combine a first error signal from a prior modulation stage of the plurality of modulation stages with a first digital signal to produce an adder signal. In some aspects, the first error signal includes a delay from the prior modulation stage. Each of the plurality of modulation stages is also configured to convert the adder signal having a first bit width into a quantized signal having a second bit width smaller than the first bit width. Each of the modulation stages is also configured to provide a second error signal based on the quantized signal to a subsequent modulation stage of the plurality of modulation stages.

First claim

What is claimed is:

1. A modulator, comprising:
a plurality of modulation stages arranged in parallel to input and output terminals of the modulator and interconnected to one another in series, wherein each of the plurality of modulation stages is configured to:
combine a first error feedback signal from a prior modulation stage of the plurality of modulation stages with a first digital input signal to produce a first adder signal, wherein the first error feedback signal includes a delay from the prior modulation stage,
convert the first adder signal having a first bit width into a quantized signal having a second bit width smaller than the first bit width,
combine a second error signal based on the quantized signal and the first adder signal to produce a second error feedback signal, and
provide the second error feedback signal to a subsequent modulation stage of the plurality of modulation stages.

2. The modulator of claim 1 , wherein each of the plurality of modulation stages is configured to perform delta-sigma modulation on the first digital signal.

3. The modulator of claim 1 , wherein one or more of the plurality of modulation stages includes a first-order delta-sigma modulator.

4. The modulator of claim 1 , wherein one or more of the plurality of modulation stages includes a second-order delta-sigma modulator.

5. The modulator of claim 1 , wherein at least one modulation stage of the plurality of modulation stages includes a plurality of quantizers and a plurality of feedback loops coupled to respective ones of the plurality of quantizers.

6. The modulator of claim 5 , wherein one or more of the plurality of feedback loops includes a first-order feedback loop filter.

7. The modulator of claim 5 , wherein one or more of the plurality of feedback loops includes a second-order feedback loop filter.

8. The modulator of claim 1 , wherein each of the plurality of modulation stages comprises:
a first adder and a second adder, the first adder being configured to combine the first error feedback signal and the first digital input signal to produce the first adder signal, the second adder being configured to combine the first adder signal and the second error signal to produce the second error feedback signal;
a quantizer coupled to the first adder and to the second adder, the quantizer being configured to generate the quantized signal from the first adder signal and provide the quantized signal to an output of the modulation stage and the second error signal to the second adder; and
a feedback loop filter configured to delay the second error feedback signal to produce the second error feedback signal.

9. The modulator of claim 1 , wherein outputs of the plurality of modulation stages having a first frequency are multiplexed to produce a serialized output having a second frequency greater than the first frequency.

10. The modulator of claim 1 , wherein each of the plurality of modulation stages is partitioned into a first stream carrying a first portion of the first digital signal that corresponds to a most-significant-bit (MSB) signal path and to a second stream carrying a second portion of the first digital signal that corresponds to a least-significant-bit (LSB) signal path.

11. The modulator of claim 10 , wherein the MSB signal path comprises an MSB extraction circuit configured to extract the first portion from the first digital input signal, the first portion having a first number of bits.

12. The modulator of claim 11 , wherein the LSB signal path comprises:
an LSB extraction circuit configured to extract the second portion from the first digital input signal, the second portion having a second number of bits smaller than the first number of bits;
a first adder and a second adder, the first adder being configured to combine the first error feedback signal and the first digital input signal to produce the first adder signal, the second adder being configured to combine the first adder signal and the second error signal to produce the second error feedback signal; and
a quantizer coupled to the first adder and to the second adder, the quantizer being configured to generate the quantized signal from the first adder signal and provide the quantized signal to an output of the modulation stage and the second error signal to the second adder.

13. The modulator of claim 12 , wherein each of the LSB extraction circuit and the MSB extraction circuit comprises:
a slicing circuit configured to partition the first digital input signal into a sliced signal having a corresponding number of bits smaller than that of the first digital signal; and
a sign operation circuit connected in series with the slicing circuit and is configured to perform a sign operation on the sliced signal.

14. The modulator of claim 12 , wherein the quantizer comprises:
a third adder configured to combine a constant value with the first adder signal to produce a third adder signal having a rounded value;
a slicing circuit configured to partition the third adder signal into a sliced quantization signal having a corresponding number of bits smaller than that of the first adder signal; and
a sign operation circuit connected in series with the slicing circuit and is configured to perform a sign operation on the sliced quantization signal.

15. The modulator of claim 12 , wherein each of the plurality of modulation stages comprises an output adder, and wherein the first portion produced along the MSB signal path is passed through to the output adder for combination with the quantized signal fed from the quantizer to produce a second digital signal.

16. The modulator of claim 12 , wherein the LSB signal path comprises a delay connected between the first and second adders.

17. The modulator of claim 12 , wherein the LSB signal path comprises a plurality of error terminals, wherein the plurality of error terminals includes a first error terminal that is connected to an error terminal of a previous modulation stage of the plurality of modulation stages and to the first adder, and wherein the plurality of error terminals includes a second error terminal that is connected to an error terminal of a subsequent modulation stage of the plurality of modulation stages and to the second adder.

18. The modulator of claim 17 , further comprising:
an output adder connected to the MSB signal path and to the LSB signal path; and
a plurality of delay blocks arranged on each of the MSB signal path and the LSB signal path, wherein the plurality of delay blocks includes a first delay block arranged between the quantizer and the output adder and a second delay block arranged between the MSB extraction circuit and the output adder.

19. The modulator of claim 1 , further comprising:
a feedback loop filter connected to a first modulation stage of the plurality of modulation stages and to a last modulation stage of the plurality of modulation stages, wherein the feedback loop filter delays an error signal from the last modulation stage and feeds a delayed error signal to the first modulation stage.

20. A delta-sigma modulation device, comprising:
means for combining a first error feedback signal from a prior modulation stage of a plurality of modulation stages arranged in parallel to one another with an input digital signal to produce an adder signal;
means for converting the adder signal having a first bit width to a quantized signal having a second bit width smaller than the first bit width;
means for combining a second error signal based on the quantized signa

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Cattivelli Federico Santiago
• Sahinoglu Gozde

Classifications

• H03M3/46

  using a combination of at least one delta-sigma modulator in series with at least one analogue/digital converter of a different type · CPC title

• H03M3/416 Primary

  all these quantisers being multiple bit quantisers · CPC title

• H03M3/448

  by removing part of the zeroes, e.g. using local feedback loops · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/42

  having multiple quantisers arranged in parallel loops · CPC title