Frequency synthesizer and method of operating the same

Patent metadata

Field	Value
Publication number	US-10666271-B1
Application number	US-201916508049-A
Country	US
Kind code	B1
Filing date	Jul 10, 2019
Priority date	May 15, 2019
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A frequency synthesizer, comprises a phase frequency detector to receive a frequency signal and a reference clock, and to output a phase difference according to a phase difference and a frequency difference between the frequency signal and the reference clock; a charge pump to generate a current according to the phase difference; a loop filter to generate a first voltage signal based on the current; a N-path filter each comprising a switch, a path filter and to generate N paths of filtered voltages based on the first voltage; a voltage control oscillator to generate a second voltage signal based on a sum of the N paths of filtered voltages; a frequency divider to generate the frequency signal based on the second voltage signal and a variable frequency dividing ratio; and a Sigma-Delta Modulator to generate the variable frequency dividing ratio based on a digital representation of a frequency fractional value and the reference clock.

First claim

What is claimed is:

1. A frequency synthesizer, comprising:
a phase frequency detector configured to receive a frequency signal and a reference clock, and to output a phase difference according to a phase difference and a frequency difference between the frequency signal and the reference clock;
a charge pump communicatively coupled to the phase frequency detector and configured to generate a current according to the phase difference;
a loop filter communicatively coupled to the charge pump and configured to generate a first voltage signal based on the current;
a N-path filter including N paths and communicatively coupled to the loop filter, each of the N paths of the N-path filter comprising a switch and a path filter, wherein the N-path filter is configured to generate N paths of filtered voltages based on the first voltage signal, wherein N is a natural number greater than 1;
a voltage control oscillator communicatively coupled to the N-path filter and configured to generate a second voltage signal based on a sum of the N paths of filtered voltages;
a frequency divider communicatively coupled to the voltage control oscillator and the phase frequency detector, and configured to generate the frequency signal based on the second voltage signal and a variable frequency dividing ratio; and
a Sigma-Delta Modulator (SDM) communicatively coupled to the frequency divider and configured to generate the variable frequency dividing ratio based on a digital representation of a frequency fractional dividing ratio and a SDM reference clock.

2. The frequency synthesizer of claim 1 , further comprising an adder communicatively coupled between the N-path filter and the voltage control oscillator and configured to generate the sum of the N paths of filtered voltages by adding the N paths of filtered voltages.

3. The frequency synthesizer of claim 1 , wherein the voltage control oscillator further comprises:
N voltage control oscillating elements, each of the N voltage control oscillating elements configured to generate an oscillated voltage signal based on a corresponding one of the N paths of filtered voltages; and
an adder communicatively coupled to the N voltage control oscillating elements and configured to generate the second voltage signal by adding the N oscillated voltage signal.

4. The frequency synthesizer of claim 1 , wherein the loop filter further comprises:
a sample switch communicatively coupled to the charge pump and configured to receive the current;
a hold switch communicatively coupled to the sample switch and a reset switch, and configured to output an internal output voltage signal, wherein the reset switch is configured to receive a first reference voltage;
a sample capacitor with a first plate communicatively coupled to a voltage reference point having a second reference voltage and a second plate communicatively coupled to the sample switch, the reset switch and the hold switch; and
a hold capacitor including a first plate communicatively coupled to the hold switch and configured to smoothen the current and a second plate communicatively coupled to the second voltage reference point.

5. The frequency synthesizer of claim 1 , wherein each path of the N-path filter comprises a second capacitor.

6. The frequency synthesizer of claim 1 , wherein each path of the N-path filter comprises a first resistor and a third capacitor connected in serial to the first resistor.

7. The frequency synthesizer of claim 1 , wherein each path of the N-path filter comprises a fourth capacitor, a second resistor, and a fifth capacitor connected in serial to the second resistor, wherein the fourth capacitor is connected in parallel to a serial combination of the second resistor and the fifth capacitor.

8. The frequency synthesizer of claim 1 , wherein a corresponding switch of each path of the N-path filter is controlled by a phase control signal of a corresponding path, wherein a phase difference between the corresponding phase control signal and a neighboring phase control signal of the corresponding phase control signal equals 2π/N.

9. A method of operating a frequency synthesizer, comprising:
receiving, by a phase frequency detector in the frequency synthesizer, a frequency signal and a reference clock;
outputting, by the phase frequency detector, a phase difference according to a phase difference and a frequency difference between the frequency signal and the reference clock;
generating, by a charge pump communicatively coupled to the phase frequency detector, a current according to the phase difference;
generating, by a loop filter communicatively coupled to the charge pump, a first voltage signal based on the current;
generating, by each of N paths of a N-path filter communicatively coupled to the loop filter, filtered voltages based on the first voltage signal, wherein each of the N paths of the N-path filter comprises a switch and a path filter, wherein N is a natural number greater than 1;
generating, by a voltage control oscillator communicatively coupled to the N-path filter, a second voltage signal based on a sum of the N paths of filtered voltages;
generating, by a frequency divider communicatively coupled to the voltage control oscillator and the phase frequency detector, the frequency signal based on the second voltage signal and a variable frequency dividing ratio; and
generating, by a Sigma-Delta Modulator (SDM) communicatively coupled to the frequency divider, the variable frequency dividing ratio based on a digital representation of a frequency fractional dividing ratio and a SDM reference clock.

10. The method of claim 9 , further comprising
generating, by an adder communicatively coupled between the N-path filter and the voltage control oscillator, the sum of the N paths of filtered voltages by adding the N paths of filtered voltages.

11. The method of claim 9 , wherein generating, by a voltage control oscillator communicatively coupled to the N-path filter, a second voltage signal based on a sum of the N paths of filtered voltages is further implemented by
generating, by each of N voltage control oscillating elements, an oscillated voltage signal based on a corresponding one of the N paths of filtered voltages; and
generating, by an adder communicatively coupled to the N voltage control oscillating elements, the second voltage signal by adding the N oscillated voltage signals.

12. The method of claim 9 , wherein generating, by a loop filter communicatively coupled to the charge pump, a first voltage signal based on the current is further implemented by:
receiving, by a sample switch communicatively coupled to the charge pump, the current;
outputting, by a hold switch communicatively coupled to the sample switch and a reset switch, an internal output voltage signal; and
receiving, by the reset switch, a reference voltage; wherein
a first plate of a first capacitor is communicatively coupled to ground and a second plate of the first capacitor is communicatively coupled to the sample switch, the reset switch and the hold switch.

13. The method of claim 12 , wherein the loop filter further comprises a Resistor-Capacitor filter communicatively coupled to the hold switch and configured to filter glitches in the current.

14. The method of claim 9 , wherein each of the N-path filter comprises a second capacitor.

15. The method of claim 9 , wherein each of the N-path filter comprises a first resistor and a third capacitor connected in serial to the first resistor.

16. The method of claim 9 , wherein each of the N-path filter comprises a fourth capacitor, a second resi

Assignees

• Beken Corp

Inventors

• Guo Dawei
• Kong Ronghui

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/1974

  for fractional frequency division · CPC title

• H03H19/002

  N-path filters · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title