Programmable input/output circuit

Patent metadata

Field	Value
Publication number	US-10666258-B2
Application number	US-201816193261-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	May 5, 2009
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

First claim

What is claimed is:

1. A programmable input/output (I/O) circuit comprising:
an output buffer coupled between an output signal and an I/O pad, the output buffer coupled to a reference voltage from a reference generator circuit;
an input comparator coupled between an input signal and the I/O pad, the input comparator comprising a first input coupled to the I/O pad;
a multiplexor coupled between a second input of the input comparator and a plurality of reference voltages generated by the reference generator circuit, wherein the multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

2. The programmable I/O circuit of claim 1 , wherein the signal for dynamically selecting a second reference voltage from the plurality of reference voltages is provided without interrupting operation of circuits coupled to the programmable I/O circuit.

3. The programmable I/O circuit of claim 1 , wherein the output buffer is a single input digital buffer coupled to an adjustable reference voltage.

4. The programmable I/O circuit of claim 1 , wherein the input comparator is an operational amplifier in an open loop configuration.

5. The programmable I/O circuit of claim 1 , wherein the plurality of reference voltages are provided from circuits disposed on the same silicon substrate as the programmable I/O circuit.

6. The programmable I/O circuit of claim 1 , wherein at least one of the plurality of reference voltages are provided from circuits disposed on different silicon substrates as the programmable I/O circuit.

7. The programmable I/O circuit of claim 1 , wherein the select signal is generated from a processing system.

8. A method for determining the logic state of a signal on an I/O pad comprising:
receiving a signal on an input;
comparing a voltage level of the signal to a reference voltage;
if the voltage level of the signal is less than the reference voltage, recognizing the signal as a logic LOW; and
if the voltage level of the signal is greater than the reference voltage, recognizing the signal as a logic HIGH,
wherein the reference voltage is provided by a reference generator circuit and is selected from a plurality of reference voltages by a select signal and wherein the reference voltage is selected dynamically during operation of an I/O circuit, and
wherein the reference generator circuit generates an output reference voltage for an output buffer coupled to the I/O pad.

9. The method for determining the logic state of a signal on an I/O pad of claim 8 , wherein the plurality of reference voltages are provided from circuits disposed on a same silicon substrate as the I/O circuit.

10. The method for determining the logic state of a signal on an I/O pad of claim 8 , wherein at least one of the plurality of reference voltages is provided from circuit disposed on a different silicon substrate as the I/O circuit.

11. The method for determining the logic state of a signal on an I/O pad of claim 8 , wherein the plurality of reference voltages are coupled to a multiplexor for receiving a select signal.

12. The method for determining the logic state of a signal on an I/O pad of claim 11 , wherein the select signal is provided by a processing system.

13. The method for determining the logic state of a signal on an I/O pad of claim 12 , wherein the processing system is one of a central processing unit, a direct memory access (DMA) controller, a programmable digital circuit, and a fixed function digital circuit.

14. A system comprising:
a processing circuit;
an output buffer coupled between an output signal and an I/O pad, the output buffer coupled to a reference voltage from a reference generator circuit;
an input comparator coupled between an input signal and the I/O pad, the input comparator comprising a first input coupled to the I/O pad;
a multiplexor coupled between a second input of the input comparator and a plurality of reference voltages generated by the reference generator circuit, wherein the multiplexor receives a select signal from the processing circuit for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

15. The programmable I/O circuit of claim 14 , wherein the signal for dynamically selecting a second reference voltage from the plurality of reference voltages is provided without interrupting operation of circuits coupled to the programmable I/O circuit.

16. The programmable I/O circuit of claim 15 , wherein the input comparator is an operational amplifier in an open loop configuration.

17. The programmable I/O circuit of claim 14 , wherein the output buffer is a single input digital buffer coupled to an adjustable reference voltage.

18. The programmable I/O circuit of claim 17 , wherein the plurality of reference voltages are provided from circuits disposed on the same silicon substrate as the programmable I/O circuit.

19. The programmable I/O circuit of claim 14 , wherein at least one of the plurality of reference voltages are provided from circuits disposed on different silicon substrates as the programmable I/O circuit.

20. The programmable I/O circuit of claim 14 , wherein the processing circuit is one of a central processing unit, a direct memory access (DMA) controller, a programmable digital circuit, and a fixed function digital circuit.

Assignees

• Cypress Semiconductor Corp

Inventors

• Williams Timothy John
• Wright David G
• Verge Gregory John
• Byrkett Bruce E

Classifications

• G06F5/065

  Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G06F13/4072

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• H03K19/017581 Primary

  programmable · CPC title