Quadrature relaxation oscillator using frequency error compensation loop

Patent metadata

Field	Value
Publication number	US-10666236-B2
Application number	US-201716469621-A
Country	US
Kind code	B2
Filing date	Nov 30, 2017
Priority date	Dec 14, 2016
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

First claim

The invention claimed is:

1. A quadrature relaxation oscillator using a frequency error compensation loop, comprising:
a charge control unit configured to provide a charge path or a discharge path for generating an I clock signal and a Q clock signal at a corresponding phase among first to fourth phases;
a charge unit configured to charge a power supply voltage supplied through the charge path or discharge a previously-charged voltage through the discharge path, and output corresponding first and second charge/discharge voltages;
a reference voltage generation unit configured to output first and second upper reference voltages and first and second lower reference voltages by applying a frequency compensation method, wherein the reference voltage generation unit compares the first and second charge/discharge voltages with upper and lower reference voltages, respectively, at phases at which levels of the first and second charge/discharge voltages are stopped, and outputs the first and second upper reference voltages and the first and second lower reference voltages which are synchronized with the first and second charge/discharge voltages;
a comparison unit configured to compare the first charge/discharge voltage with the first upper and lower reference voltages and compare the second charge/discharge voltage with the second upper and lower reference voltages, and output corresponding respective logic signals; and
an S-R latch unit configured to latch the respective logic signals and output the I clock signal and the Q clock signal corresponding thereto.

2. The quadrature relaxation oscillator of claim 1 , wherein the charge control unit comprises:
a first charge control unit including a first PMOS transistor which provides a charge path to supply the power supply voltage as a charge voltage at the first phase and a first NMOS transistor which provides a discharge path to discharge the previously-charged voltage at the third phase; and
a second charge control unit including a second PMOS transistor which provides a charge path to supply the power supply voltage as a charge voltage at the second phase and a second NMOS transistor which provides a discharge path to discharge the previously-charged voltage at the fourth phase.

3. The quadrature relaxation oscillator of claim 1 , wherein the charge unit comprises:
a first charge unit including a first resistor and a first capacitor which are coupled in series between a first charge/discharge node of the charge control unit and a ground terminal, and configured to output the first charge/discharge voltage; and
a second charge unit including a second resistor and a second capacitor which are coupled in series between a second charge/discharge node of the charge control unit and the ground terminal, and configured to output the second charge/discharge voltage.

4. The quadrature relaxation oscillator of claim 1 , wherein the reference voltage generation unit comprises:
a first frequency error compensation loop configured to compensate for a frequency error and output the first and second upper reference voltages synchronized with the first and second charge/discharge voltages;
a second frequency error compensation loop configured to compensate for a frequency error and output the first and second lower reference voltages synchronized with the first and second charge/discharge voltages;
a reference voltage generation circuit configured to output the upper reference voltage and the lower reference voltage by using resistors coupled in series between the power supply voltage and the ground terminal; and
a switching control signal generation unit configured to output switching control signals for controlling switching operations of switches included in the first and second frequency error compensation loops.

5. The quadrature relaxation oscillator of claim 4 , wherein the first frequency error compensation loop comprises:
a first sampling unit configured to select and sample the first charge/discharge voltage and the upper reference voltage at the second phase, and select and sample the second charge/discharge voltage and the upper reference voltage at the third phase;
a first amplifier configured to convert and amplify a voltage sampled by the first sampling unit into a current;
a first sub amplifier configured to cause an output voltage of the first amplifier to have a level similar to the first upper reference voltage; and
a first error compensation unit configured to update the first and second upper reference voltages with the output current of the first amplifier, after the output voltage of the first amplifier is caused to have a level similar to the first upper reference voltage.

6. The quadrature relaxation oscillator of claim 4 , wherein the second frequency error compensation loop comprises:
a second sampling unit configured to select and sample the first charge/discharge voltage and the lower reference voltage at the fourth phase, and select and sample the second charge/discharge voltage and the lower reference voltage at the first phase;
a second amplifier configured to convert and amplify a voltage sampled by the second sampling unit into a current;
a second sub amplifier configured to cause an output voltage of the second amplifier to have a level similar to the first lower reference voltage; and
a second error compensation unit configured to update the first and second lower reference voltages with the output current of the second amplifier, after the output voltage of the second amplifier is caused to have a level similar to the first lower reference voltage.

7. The quadrature relaxation oscillator of claim 1 , wherein the comparison unit comprises:
a first comparison unit including first and second comparators which compare the first charge/discharge voltage with the first upper and lower reference voltages and output corresponding respective logic signals; and
a second comparison unit including third and fourth comparators which compare the second charge/discharge voltage with the first and second lower reference voltages and output corresponding respective logic signals.

8. The quadrature relaxation oscillator of claim 7 , wherein the S-R latch unit comprises:
a first S-R latch configured to receive a logic signal outputted from the first comparator through a set terminal thereof, receive a logic signal outputted from the second comparator through a reset terminal thereof, and output the I clock signal; and
a second S-R latch configured to receive a logic signal outputted from the third comparator through a set terminal thereof, receive a logic signal outputted from the fourth comparator through a reset terminal thereof, and output the Q clock signal.

Assignees

• Postech Acad Ind Found

Inventors

• Sim Jae Yoon
• Koo Ja Hyun

Classifications

• H03K3/011

  Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} · CPC title

• H03K3/0231 Primary

  Astable circuits {(H03K3/0315 takes precedence)} · CPC title

• H03K4/94

  having trapezoidal shape · CPC title

• H03K3/02315 Primary

  Stabilisation of output, e.g. using crystal · CPC title

• H03K4/52

  using two semiconductor devices so coupled that the input of each one is derived from the output of the other, e.g. multivibrator · CPC title