Gate-controlled bipolar junction transistor and operation method thereof

Patent metadata

Field	Value
Publication number	US-10665690-B2
Application number	US-201816163551-A
Country	US
Kind code	B2
Filing date	Oct 17, 2018
Priority date	Oct 1, 2018
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A gate-controlled bipolar junction transistor includes a substrate, an emitter region, a base region disposed on one side of the emitter region, and a collector region disposed on one side of the base region and being opposite to the emitter region. The emitter region includes first fin structures, first metal gates extending across the first fin structures, and an emitter contact plug on the first fin structures. A gate contact region is disposed between the emitter region and the base region. Each of the first metal gates includes an extended contact end portion protruding toward the base region. The extended contact end portion is disposed within the gate contact region. A gate contact is disposed on the extended contact end portion.

First claim

What is claimed is:

1. A gate-controlled bipolar junction transistor, comprising:
a substrate;
an emitter region disposed on the substrate, the emitter region comprising a plurality of first fins structures extending along a first direction, at least two first metal gates extending across the plurality of first fin structures along a second direction, and an emitter contact plug on the plurality of first fin structures elongating along the second direction between the at least two first metal gates;
a base region disposed on one side of the emitter region;
a gate contact region disposed between the emitter region and the base region, wherein the each of the at least two first metal gates comprises an extended contact end portion protruding toward the base region and being disposed within the gate contact region;
a gate contact plug disposed on the extended contact end portion; and
a collector region disposed on one side of the base region and being opposite to the emitter region, wherein the collector region is annular and comprising at least one third fin structure extending along the first direction, and height of the at least one third fin structure in the collector region is less than height of one of the first fin structures in the emitter region.

2. The gate-controlled bipolar junction transistor according to claim 1 , wherein the emitter contact plug is electrically connected to an emitter line overlying the emitter region.

3. The gate-controlled bipolar junction transistor according to claim 2 , wherein the gate contact plug is electrically connected to a gate line overlying the gate contact region.

4. The gate-controlled bipolar junction transistor according to claim 3 , wherein in operation a negative gate voltage or a positive gate voltage is applied to the at least two first metal gates via the gate line and the gate contact region.

5. The gate-controlled bipolar junction transistor according to claim 3 , wherein the gate line and the emitter line are disposed in different levels of a metal interconnection scheme on the substrate.

6. The gate-controlled bipolar junction transistor according to claim 1 , wherein the base region comprising at least one second fin structure extending along the first direction, at least two second metal gates extending across the at least one second fin structure along the second direction, and a base contact plug on the at least one second fin structure between the at least two second metal gates.

7. The gate-controlled bipolar junction transistor according to claim 6 , wherein the at least two first metal gates are aligned with the at least two second metal gates, respectively, along the second direction.

8. The gate-controlled bipolar junction transistor according to claim 6 , wherein the at least two second metal gates are not in contact with the at least two first metal gates.

9. The gate-controlled bipolar junction transistor according to claim 1 , wherein the substrate is a semiconductor substrate of a first conductivity type, a first ion well of the first conductivity type is provided in the substrate, wherein the emitter region and the base region are disposed in the first ion well.

10. The gate-controlled bipolar junction transistor according to claim 9 , wherein the collector region is disposed in a second ion well of a second conductivity type surrounding the first ion well.

11. A gate-controlled bipolar junction transistor, comprising:
a substrate;
an emitter region disposed on the substrate, the emitter region comprising a plurality of first fins structures extending along a first direction, at least two first metal gates extending across the plurality of first fin structures along a second direction, and an emitter contact plug on the plurality of first fin structures elongating along the second direction between the at least two first metal gates;
a base region disposed on one side of the emitter region;
a gate contact region disposed between the emitter region and the base region, wherein the each of the at least two first metal gates comprises an extended contact end portion protruding toward the base region and being disposed within the gate contact region;
a gate contact plug disposed on the extended contact end portion; and
a collector region disposed on one side of the base region and being opposite to the emitter region, wherein one side of the first metal gate is aligned with one side of the first fin structure without any overhang of the first metal gate.

12. A gate-controlled bipolar junction transistor, comprising:
a substrate;
an emitter region disposed on the substrate, the emitter region comprising a plurality of first fins structures extending along a first direction, at least two first metal gates extending across the plurality of first fin structures along a second direction, and an emitter contact plug on the plurality of first fin structures elongating along the second direction between the at least two first metal gates;
a base region disposed on one side of the emitter region;
a gate contact region disposed between the emitter region and the base region, wherein the each of the at least two first metal gates comprises an extended contact end portion protruding toward the base region and being disposed within the gate contact region;
a gate contact plug disposed on the extended contact end portion; and
a collector region disposed on one side of the base region and being opposite to the emitter region, wherein the two first metal gates are connected together by an interconnect, the interconnect extends along the first direction, and the gate contact plug is electrically connected to the interconnect.

Assignees

• United Microelectronics Corp

Inventors

• Pan Chen-Wei
• Cho Sheng

Classifications

• H01L29/66265

  Electricity · mapped topic

• H01L29/735

  Electricity · mapped topic

• H01L29/0808

  Electricity · mapped topic

• H01L29/41708

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic