Shift register and driving method therefor, and display device

Patent metadata

Field	Value
Publication number	US-10665191-B2
Application number	US-201715750679-A
Country	US
Kind code	B2
Filing date	Jun 27, 2017
Priority date	Oct 26, 2016
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A shift register and driving method therefore, and a display device are provided. The shift register includes: an input circuit; an output circuit; a reset circuit; a pull-down circuit; a pull-down control circuit; and a first noise reduction circuit. The first noise reduction circuit is coupled to a second input terminal of the shift register, a first input terminal, an output terminal and a first supply voltage terminal. The shift register can effectively reduce noise at the output terminal.

First claim

What is claimed is:

1. A shift register, comprising:
an input circuit, a first terminal of the input circuit being coupled to a first input terminal of the shift register and configured to receive a first input signal from the first input terminal, a second terminal of the input circuit being coupled to a pull-up node, and a third terminal of the input circuit being coupled to a first clock signal terminal;
an output circuit, a first terminal of the output circuit being coupled to a second clock signal terminal, a second terminal of the output circuit being coupled to the pull-up node, and a third terminal of the output circuit being coupled to an output terminal of the shift register;
a pull-down circuit, a first terminal of the pull-down circuit being coupled to a pull-down node, a second terminal of the pull-down circuit being coupled to the output terminal of the shift register, a third terminal of the pull-down circuit being coupled to the pull-up node, and a fourth terminal of the pull-down circuit being coupled to a first supply voltage terminal;
a pull-down control circuit, a first terminal of the pull-down control circuit being coupled to the first clock signal terminal, a second terminal of the pull-down control circuit being coupled to the second clock signal terminal, a third terminal of the pull-down control circuit being coupled to the pull-down node, a fourth terminal of the pull-down control circuit being coupled to the first supply voltage terminal, and a fifth terminal of the pull-down control circuit being coupled to the pull-up node; and
a first noise reduction circuit, a first terminal of the first noise reduction circuit being coupled to a second input terminal of the shift register and configured to receive a second input signal from the second input terminal, a second terminal of the first noise reduction circuit being coupled to the first input terminal of the shift register and configured to receive the first input signal from the first input terminal, a third terminal of the first noise reduction circuit being coupled to the output terminal of the shift register, a fourth terminal of the first noise reduction circuit being coupled to the first supply voltage terminal, and the first noise reduction circuit being configured to continuously reduce noise at the output terminal of the shift register when there is no input signal from the first input terminal and the second input terminal.

2. The shift register according to claim 1 , further comprising a second noise reduction circuit,
wherein a first terminal of the second noise reduction circuit is coupled to the first clock signal terminal, a second terminal of the second noise reduction circuit is coupled to the output terminal of the shift register, and a third terminal of the second noise reduction circuit is coupled to the first supply voltage terminal.

3. The shift register according to claim 2 , wherein the second noise reduction circuit comprises a third noise reduction transistor, a gate electrode of the third noise reduction transistor is coupled to the first clock signal terminal, a first electrode of the third noise reduction transistor is coupled to the output terminal, and a second electrode of the third noise reduction transistor is coupled to the first supply voltage terminal.

4. The shift register according to claim 1 , wherein the first noise reduction circuit comprises:
a first noise reduction transistor, a gate electrode of the first noise reduction transistor being coupled to the second input terminal, and a first electrode of the first noise reduction transistor being coupled to the output terminal; and
a second noise reduction transistor, a gate electrode of the second noise reduction transistor being coupled to the first input terminal, a first electrode of the second noise reduction transistor being coupled to a second electrode of the first noise reduction transistor, and a second electrode of the second noise reduction transistor being coupled to the first supply voltage terminal.

5. The shift register according to claim 4 , wherein the first noise reduction transistor and the second noise reduction transistor are P-type transistors, and other transistors are all N-type transistors.

6. The shift register according to claim 1 , wherein the input circuit comprises:
a first input transistor, a gate electrode and a first electrode of the first input transistor being coupled to the first input terminal, and a second electrode of the first input transistor being coupled to the pull-up node; and
a second input transistor, a gate electrode of the second input transistor being coupled to the first clock signal terminal, a first electrode of the second input transistor being coupled to the first input terminal, and a second electrode of the second input transistor being coupled to the pull-up node.

7. The shift register according to claim 1 , wherein the output circuit comprises:
an output transistor, a gate electrode of the output transistor being coupled to the pull-up node, a first electrode of the output transistor being coupled to the second clock signal terminal, and a second electrode of the output transistor being coupled to the output terminal; and
a first capacitor, a first end of the first capacitor being coupled to the pull-up node, and a second end of the first capacitor being coupled to the output terminal.

8. The shift register according to claim 1 , wherein the pull-down circuit comprises:
a node pull-down transistor, a gate electrode of the node pull-down transistor being coupled to the pull-down node, a first electrode of the node pull-down transistor being coupled to the pull-up node, and a second electrode of the node pull-down transistor being coupled to the first supply voltage terminal; and
an output pull-down transistor, a gate electrode of the output pull-down transistor being coupled to the pull-down node, a first electrode of the output pull-down transistor being coupled to the output terminal, and a second electrode of the output pull-down transistor being coupled to the first supply voltage terminal.

9. The shift register according to claim 1 , wherein the pull-down control circuit comprises:
a first pull-down control transistor, a gate electrode of the first pull-down control transistor being coupled to a pull-down control node, a first electrode of the first pull-down control transistor being coupled to the second clock signal terminal, and a second electrode of the first pull-down control transistor being coupled to the pull-down node;
a second pull-down control transistor, a gate electrode of the second pull-down control transistor being coupled to the pull-up node, a first electrode of the second pull-down control transistor being coupled to the pull-down node, and a second electrode of the second pull-down control transistor being coupled to the first supply voltage terminal;
a third pull-down control transistor, a gate electrode of the third pull-down control transistor being coupled to the first clock signal terminal, a first electrode of the third pull-down control transistor being coupled to the pull-down node, and a second electrode of the third pull-down control transistor being coupled to the first supply voltage terminal;
a fourth pull-down control transistor, a gate electrode of the fourth pull-down control transistor being coupled to the first clock signal terminal, a first electrode of the fourth pull-down control transistor being coupled to the pull-down control node, and a second electrode of the fourth pull-down control transistor being coupled to the first supply voltage terminal; and
a fifth pull-down control transistor, a gate electrode and a first electrode of the fifth pull-down contro

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Wang Guangxing
• Zhang Bin
• Dong Dianzheng
• Zhang Qiang
• Chen Pengming
• Zhang Kan
• Xie Yu
• Wang Zheng

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title