Testbench restoration based on capture and replay

Patent metadata

Field	Value
Publication number	US-10664637-B2
Application number	US-201514981524-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

Messages transmitted from an emulator to a testbench of a part of the testbench are recorded from a starting point of an emulation operation to a checkpoint of the emulation operation. State information of the emulator at the checkpoint is captured and stored. The emulator is then configured to a state corresponding to the checkpoint based on the stored state information, and the testbench or the part of the testbench is restored to the checkpoint by running the testbench or the part of the testbench based on the recorded messages.

First claim

What is claimed is:

1. A method, comprising:
recording messages transmitted from an emulator to a testbench or a part of the testbench from a starting point of an emulation operation to a checkpoint of the emulation operation, wherein the emulator is loaded with a design under verification (DUV) and the testbench or part of the testbench is separate from the DUV;
capturing and storing state information of the emulator at the checkpoint, the state information comprising signal values of state elements at the checkpoint;
configuring the emulator to a state corresponding to the checkpoint based on the stored state information; and
restoring the testbench or the part of the testbench to the checkpoint by running the testbench or the part of the testbench based on the recorded messages.

2. The method recited in claim 1 , further comprising:
running the emulator along with the testbench or the part of the testbench starting from the checkpoint.

3. The method recited in claim 1 , wherein the testbench or the part of the testbench is a standalone software model, a set of multiple connected software models, a testbench running on a software simulator, or a system including one or more connected software models and a testbench running on a software simulator.

4. The method recited in claim 1 , wherein a verification model implemented in the emulator represents a design of a processor, and the emulation operation performed by the verification model between the starting pointing and the checkpoint comprises a booting process of the processor.

5. The method recited in claim 1 , further comprising:
recording output messages transmitted from the testbench or the part of the testbench to the emulator from the starting point of the emulation operation to the checkpoint of the emulation operation; and
comparing output messages transmitted from the testbench or the part of the testbench to the emulator during the restoring with the recorded output messages.

6. The method recited in claim 1 , wherein the recorded messages do not include messages transmitted to another part of the testbench that is mapped to the emulator.

7. A system, comprising:
an emulator and a workstation coupled to the emulator, the emulator and the workstation being configured to perform a method, the method comprising:
recording messages transmitted from an emulator to a testbench or a part of the testbench from a starting point of an emulation operation to a checkpoint of the emulation operation, wherein the emulator is loaded with a design under verification (DUV) and the testbench or the part of the testbench is separate from the DUV and implemented by the workstation;
capturing and storing state information of the emulator at the checkpoint, the state information comprising signal values of state elements at the checkpoint;
configuring the emulator to a state corresponding to the checkpoint based on the stored state information; and
restoring the testbench or the part of the testbench to the checkpoint by running the testbench or the part of the testbench based on the recorded messages.

8. The system recited in claim 7 , wherein the method further comprises:
running the emulator along with the testbench or the part of the testbench starting from the checkpoint.

9. The system recited in claim 7 , wherein the testbench or the part of the testbench is a standalone software model, a set of multiple connected software models, a testbench running on a software simulator, or a system including one or more connected software models and a testbench running on a software simulator.

10. The system recited in claim 7 , wherein a verification model implemented in the emulator represents a design of a processor, and the emulation operation performed by the verification model between the starting pointing and the checkpoint comprises a booting process of the processor.

11. The system recited in claim 7 , wherein the method further comprises:
recording output messages transmitted from the testbench or the part of the testbench to the emulator from the starting point of the emulation operation to the checkpoint of the emulation operation; and
comparing output messages transmitted from the testbench or the part of the testbench to the emulator during the restoring with the recorded output messages.

12. The system recited in claim 7 , wherein the recorded messages do not include messages transmitted to another part of the testbench that is mapped to the emulator.

13. A non-transitory computer readable medium comprising instructions that, when executed by a processor, cause a computing system to:
configure an emulator to a state corresponding to a checkpoint of an emulation operation based on stored state information of the emulator, wherein the emulator is loaded with a design under verification (DUV) and the stored state information is captured and stored at the checkpoint during performing the emulation operation; and
restore a testbench or a part of the testbench to the checkpoint by running the testbench or the part of the testbench based on recorded messages, wherein:
the testbench or part of the testbench is separate from the DUV; and
the recorded messages are messages transmitted from the emulator to the testbench or the part of the testbench from a starting point of the emulation operation to the checkpoint of the emulation operation and are recorded during the performing the emulation operation.

14. The non-transitory computer readable medium recited in claim 13 , wherein the instructions, when executed, further cause the computing system to:
run the emulator along with the testbench or the part of the testbench starting from the checkpoint.

15. The non-transitory computer readable medium recited in claim 13 , wherein the testbench or the part of the testbench is a standalone software model, a set of multiple connected software models, a testbench running on a software simulator, or a system including one or more connected software models and a testbench running on a software simulator.

16. The non-transitory computer readable medium recited in claim 13 , wherein a verification model implemented in the emulator represents a design of a processor, and the emulation operation performed by the verification model between the starting pointing and the checkpoint comprises a booting process of the processor.

17. The non-transitory computer readable medium recited in claim 13 , wherein the instructions, when executed, further cause the computing system to:
compare output messages transmitted from the testbench or the part of the testbench to the emulator during the restoring with stored output messages, the stored output messages being recorded during the performing the emulation operation.

18. The non-transitory computer readable medium recited in claim 13 , wherein the recorded messages do not include messages transmitted to another part of the testbench that is mapped to the emulator.

Assignees

• Mentor Graphics Corp

Inventors

• Krishnamurthy Suresh
• Prakash Ruchir
• Evans Jeffrey W
• Garg Deepak Kumar

Classifications

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title