Pin number definition based analytics

Patent metadata

Field	Value
Publication number	US-10664636-B2
Application number	US-201715848945-A
Country	US
Kind code	B2
Filing date	Dec 20, 2017
Priority date	Dec 20, 2017
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

Method and apparatus for analyzing an electrical circuit design includes storing within a memory associated with a pin, a pin functional definition comprising a pin connection parameter, and comparing the pin connection parameter to a design parameter to determine a result pertaining to a pin connection. The memory may be internal or external to the pin.

First claim

What is claimed is:

1. A method of analyzing an electrical circuit design, the method comprising:
storing within a memory located internal to a pin, a pin functional definition comprising a pin connection parameter; and
comparing the pin connection parameter to a design parameter to determine a result pertaining to a pin connection.

2. The method of claim 1 , wherein the memory is stored internal to the pin.

3. The method of claim 1 , wherein the pin connection parameter includes at least one of: a bus type, a port number, a port byte, a nibble, a bit number, a net type, a pair polarity assignment scheme, a pin number, and peripheral component interconnect express (PCIe) blocking cap information.

4. The method of claim 1 , wherein determining the result further includes validating the pin connection.

5. The method of claim 1 , wherein determining the result further includes generating a wiring constraint of a net trace connection.

6. The method of claim 5 , wherein the wiring constraint is at least one of: a line width, a gap width, a tolerance allowance, a net bus generation, an inter-differential pair, an adjacent net and group spacing Inter-differential pair, an adjacent net and group spacing, a skew, a neckdown and overall length, and a line spacing.

7. The method of claim 1 , wherein determining the result further includes verifying a physical implementation of net etch traces.

8. The method of claim 1 , wherein the pin connection parameter includes at least one of: a wiring escape angle, length and trace width used, a padstack geometry, a total length, a neckdown length, a number and length of a stub, and an orthogonal wiring length.

9. The method of claim 1 , wherein determining the result further includes generating a logical connection.

10. The method of claim 1 , wherein determining the result is does not require a net name.

11. The method of claim 1 , wherein determining the result further includes determining an attenuation loss.

12. A system, comprising:
a pin;
a memory storing a pin connection parameter associated with the pin, wherein the memory is located internal to the pin; and
a processor configured to access the memory and to execute program code to compare the pin connection parameter to a design parameter to determine a result pertaining to a pin connection.

13. The system of claim 12 , wherein the pin connection parameter includes at least one of: a bus type, a port number, a port byte, a nibble, a bit number, a net type, a pair polarity assignment scheme, a pin number, and peripheral component interconnect express (PCIe) blocking cap information.

14. The system of claim 12 , wherein determining the result further includes at least one of: validating the pin connection, generating a wiring constraint of a net trace connection, and verifying a physical implementation of net etch traces.

15. The system of claim 12 , wherein determining the result further includes at least one of: determining the result further includes generating a logical connection, and determining an attenuation loss.

16. A computer program product for analyzing an electrical circuit, the computer program product comprising:
a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to:
store a pin functional definition comprising a pin connection parameter within a memory, wherein the memory is internal to the pin; and
compare the pin connection parameter to a design parameter to determine a result pertaining to a pin connection.

17. The computer program product of claim 16 , wherein the pin connection parameter includes at least one of: a bus type, a port number, a port byte, a nibble, a bit number, a net type, a pair polarity assignment scheme, a pin number, and peripheral component interconnect express (PCIe) blocking cap information.

18. The computer program product of claim 16 , wherein determining the result further includes at least one of: validating the pin connection, generating a wiring constraint of a net trace connection, and verifying a physical implementation of net etch traces.

19. The computer program product of claim 16 , wherein determining the result further includes at least one of: determining the result further includes generating a logical connection, and determining an attenuation loss.

20. The computer program product of claim 16 , wherein determining the result further includes generating a logical connection.

Assignees

• IBM

Inventors

• Hodge Damon G
• Montanez Jesus
• Win Si T

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2213/0024

  Peripheral component interconnect [PCI] · CPC title

• G06F30/30 Primary

  Circuit design · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title