Performance booster with resolution of picket-fence I/O flushing in a storage system with heterogeneous I/O workloads

Patent metadata

Field	Value
Publication number	US-10664412-B2
Application number	US-201715796413-A
Country	US
Kind code	B2
Filing date	Oct 27, 2017
Priority date	Oct 27, 2017
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

Systems and methods that select a cache flushing algorithm are provided. A stripe that spans multiple storage devices and includes a plurality of segments is provided. The stripe also includes dirty data stored in a picket-fence pattern in at least a subset of segments in the plurality of segments. A memory cache that stores data separately from the plurality of storage devices and a metadata cache that stores metadata associated with the dirty data are also provided. A cache flushing algorithm is selected using the metadata. The selected cache flushing algorithm flushes data from the memory cache to the stripe.

First claim

What is claimed is:

1. A method comprising:
storing metadata in a metadata cache, wherein the metadata identifies location of dirty data stored in a stripe that results from an input/output request, wherein the stripe spans a plurality of storage devices and includes a plurality of segments and the dirty data is included in at least one segment in the plurality of segments;
storing data in a memory cache that is separate from the plurality of storage devices;
selecting a cache flushing algorithm based on a cost of a read-write-modify algorithm, where the cost of the read-write-modify algorithm is determined using the metadata, and based on a cost of a full stripe write algorithm; and
flushing the data from the memory cache to the stripe using the selected cache flushing algorithm.

2. The method of claim 1 , wherein the metadata stores a flag identifying whether the dirty data within the at least one segment is contiguous or non-contiguous.

3. The method of claim 1 , wherein the metadata stores an average size of I/O that creates dirty data within the at least one segment.

4. The method of claim 1 ,
wherein the cost of the read-write-modify algorithm is the cost of the read-write-modify algorithm with a full segment write of the dirty data into the at least one segment and the metadata identifies that the dirty data is contiguous.

5. The method of claim 1 , wherein the cost of the read-write-modify algorithm is the cost of the read-write-modify algorithm without a full segment write of the dirty data into the at least one segment and the metadata identifies that the dirty data is contiguous.

6. The method of claim 1 , wherein the cost of the read-write-modify algorithm is the cost of the read-write-modify algorithm using a number of the plurality of storage devices where the metadata identifies that the dirty data is non-contiguous and a number of dirty data blocks that include the dirty data in the stripe.

7. The method of claim 1 , wherein the selecting further comprises:
selecting an algorithm loaded into firmware of a storage controller to flush the data from the memory cache when the dirty data is contiguous.

8. The method of claim 1 , wherein the selecting further comprises:
selecting the read-write-modify algorithm to flush the data from the memory cache when an average I/O size that created the dirty data is below an I/O size threshold and the metadata identifies that the dirty data is non-contiguous.

9. The method of claim 1 , wherein the selecting further comprises:
selecting the cache flushing algorithm based on a number of contiguous ranges of clean data within the stripe and an average I/O size that created the dirty data in the stripe being above an I/O size threshold.

10. The method of claim 1 , wherein the dirty data in the stripe is in a picket-fence pattern.

11. A computing device comprising:
a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of selecting a cache flushing algorithm; and
a processor coupled to the memory, the processor configured to execute the machine executable code to cause the processor to:
store metadata in a metadata cache, wherein the metadata includes an indication that dirty data stored in a stripe is contiguous or non-contiguous, wherein the stripe spans a plurality of storage devices and includes a plurality of segments and the dirty data is included in at least one segment in the plurality of segments;
store data in a memory cache that is separate from the plurality of storage devices;
select the cache flushing algorithm based on a cost of a read-write-modify algorithm, wherein the cost of the read-write-modify algorithm is determined using the indicator in the metadata, and based on a cost of a full stripe write algorithm; and
flush the data from the memory cache using the cache flushing algorithm.

12. The computing device of claim 11 , wherein the dirty data that is non-contiguous is spread out throughout the plurality of segments in the stripe.

13. The computing device of claim 11 , wherein the dirty data that is contiguous is stored entirely in the at least one segment in the plurality of segments.

14. The computing device of claim 11 , wherein
the cost of the read-write-modify algorithm is the cost of the read-write-modify algorithm with a full segment write of the dirty data into the at least one segment when the indication indicates that the dirty data is contiguous.

15. The computing device of claim 11 , wherein
the cost of the read-write-modify algorithm is the cost of the read-write-modify algorithm without a full segment write of the dirty data into the at least one segment when the indication indicates that the dirty data is contiguous.

16. The computing device of claim 11 , wherein the processor is further configured to execute the machine executable code to cause the processor to select an algorithm loaded into storage controller to flush the data from the memory cache when the indication in the metadata indicates that the dirty data is contiguous.

17. The computing device of claim 11 , wherein the processor is further configured to execute the machine executable code to cause the processor to further select the read-write-modify algorithm to flush the data from the memory cache when an average I/O size that created the dirty data is below an I/O size threshold.

18. A non-transitory machine readable medium having stored thereon instructions for performing a method comprising machine executable code which when executed by at least one machine, causes the machine to:
store metadata in a metadata cache, wherein the metadata identifies location of dirty data stored in a stripe that results from an input/output request, wherein the stripe spans a plurality of storage devices and comprises a plurality of segments and the dirty data is stored in a picket-fence pattern in at least one segment in the plurality of segments;
store data in a memory cache that is separate from the plurality of storage devices;
select a cache flushing algorithm based on a cost of a read-write-modify algorithm, wherein the cost of the read-write-modify algorithm is determined using the metadata, and based on a cost of a full stripe write algorithm; and
flush the data from the memory cache to the stripe using the cache flushing algorithm.

19. The non-transitory machine readable medium of claim 18 , wherein the metadata stores a logical block address range of the dirty data.

20. The non-transitory machine readable medium of claim 18 , wherein the metadata stores a flag identifying whether the dirty data is contiguous or non-contiguous and the cost of the read-write-modify algorithm is determined by accessing the flag.

Assignees

• Netapp Inc

Inventors

• Jibbe Mahmoud K
• Lang Dean
• Terrill Scott
• Buller Matthew
• Fowler Jeffery

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F2212/604

  Details relating to cache allocation · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F12/128 Primary

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title