Power efficient processor architecture

Patent metadata

Field	Value
Publication number	US-10664039-B2
Application number	US-201816043738-A
Country	US
Kind code	B2
Filing date	Jul 24, 2018
Priority date	Sep 6, 2011
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A non-transitory computer readable storage medium comprising a set of instructions which, when executed by one or more processors, causes a mobile system to:
migrate a task from a second set of processor cores to a first set of processor cores when it is determined that a value, associated with execution duration of the task, exceeds a threshold time
wherein:
each processor core of the first set has a first size, and wherein the first set includes a first cache;
each processor core of the second set has a second size, wherein the first size is larger than the second size, and wherein the second set includes a second cache; and

the first set of processor cores is coupled to the second set of processor cores through an interconnect and via the first and second caches of the first and second set, respectively, wherein an operating system (OS) is aware of tasks to be scheduled on the first and second sets of processor cores, and wherein the OS is to use a history of the task to determine which one of the processor cores of the first or second set to wake up from a low power state.

2. A system on chip (SoC) comprising:
a first set of processor cores, wherein each processor core of the first set has a first size, and wherein the first set includes a first cache;
a second set of processor cores, wherein each processor core of the second set has a second size, wherein the first size is larger than the second size, and wherein the second set includes a second cache; and
wherein a scheduler is to migrate a task from the second set to the first set when it is determined that a value, associated with execution duration of the task, exceeds a threshold time, wherein an operating system (OS) is aware of tasks to be scheduled on the first and second sets of processor cores, and wherein the OS is to use a history of the task to determine which one of the processor cores of the first or second set to wake up from a low power state.

3. The SoC of claim 2 , wherein a processor core of the first set is woken up when it is determined that the processor core of the first set is woken up most of the time upon resume.

4. The SoC of claim 2 , wherein a processor core of the first set is woken up when it is determined that the task upon resume periodically ran on the processor core of the first set.

5. A mobile phone comprising:
a system on chip (SoC) including:
a first set of processor cores, wherein each processor core of the first set has a first size, and wherein the first set includes a first cache; and
a second set of processor cores, wherein each processor core of the second set has a second size, wherein the first size is larger than the second size, and wherein the second set includes a second cache; and

a scheduler to execute on the SoC, wherein the scheduler is to migrate a task from the second set to the first set when it is determined that a value, associated with execution duration of the task, exceeds a threshold time, wherein the scheduler is to use a history of the task to determine which one of the processor cores of the first or second set to wake up from a low power state.

6. The mobile phone of claim 5 , wherein a processor core of the first set is woken up when it is determined that the processor core of the first set is woken up most of the time upon resume.

7. The mobile phone of claim 5 , wherein a processor core of the first set is woken up when it is determined that the task upon resume periodically ran on the processor core of the first set.

Assignees

• Intel Corp

Inventors

• Herdrich Andrew J
• Illikkal Rameshkumar G
• Iyer Ravishankar
• Srinivasan Sadagopan
• Moses Jaideep
• Makineni Srihari

Classifications

• G06F1/3293 Primary

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title