Display substrate, its manufacturing method, and display device

Patent metadata

Field	Value
Publication number	US-10663820-B2
Application number	US-201314381823-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Aug 22, 2013
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A method for manufacturing a display substrate includes a step of forming a pattern of a barrier layer and a pattern of a first electrode. The step of forming the pattern of the barrier layer and the pattern of the first electrode includes: forming a barrier layer film and a first electrode film sequentially; and forming the pattern of the barrier layer and the pattern of the first electrode by a single patterning process.

First claim

What is claimed is:

1. A method for manufacturing a display substrate, comprising:
a first step of forming a pattern of a gate insulating layer and a pattern of an active layer on a base substrate;
a second step of forming a barrier layer film and a pixel electrode film sequentially on the base substrate obtained after the first step;
a third step of forming a pattern of a barrier layer and a pattern of a pixel electrode by a single patterning process,
a fourth step of forming a source electrode of a thin film transistor and a drain electrode of the thin film transistor on the base substrate with the pattern of the barrier and the pattern of the pixel electrode,
wherein the pattern of the barrier layer comprises a first via-hole region, a second via-hole region, a first thickness region, and a second thickness region;
the first via-hole region of the pattern of the barrier layer comprises a pattern of a first via-hole that penetrates the pattern of the barrier layer so as to expose a first part of the pattern of the active layer, and the pattern of the source electrode is connected to the first part of the pattern of the active layer through the first via-hole;
the second via-hole region of the pattern of the barrier layer comprises a pattern of a second via-hole that penetrates the pattern of the barrier layer so as to expose a second part of the pattern of the active layer, and the pattern of the drain electrode is connected to the second part of the pattern of the active layer through the second via-hole;
the first thickness region of the pattern of the barrier layer is located above the pattern of the gate insulating layer and an orthographic projection of the pattern of the pixel electrode on the base substrate is same as that of the first thickness region of the pattern of the barrier layer;
the second thickness region of the pattern of the barrier layer is a remaining region of the pattern of the barrier layer other than the first via-hole region, the second via-hole region, and the first thickness region, a thickness of the second thickness region is less than that of the first thickness region, and an entirety of a remaining portion of the pattern of the active layer not exposed by the pattern of the first via-hole and the pattern of the second via-hole is covered by the second thickness region;
a portion of the pattern of the drain electrode is arranged on a portion of the pattern of the pixel electrode; and
the pattern of the pixel electrode is located above the first thickness region of the pattern of the barrier layer, and an outermost boundary of the pattern of the pixel electrode is a same as that of the first thickness region.

2. The method according to claim 1 , wherein the third step comprises:
a step of coating a positive photoresist onto the pixel electrode film;
a step of exposing the photoresist so as to form an unexposed region corresponding to a region where the pattern of the pixel electrode is located, a fully-exposed region corresponding to a region where the pattern of the first via-hole is located and a region where the pattern of the second via-hole is located, and a partially-exposed region corresponding to a region other than the region where the pattern of the pixel electrode is located, the region where the pattern of the first via-hole is located, and the region where the pattern of the second via-hole is located;
a step of developing the photoresist so that a thickness of the photoresist at the unexposed region remains unchanged so as to form a photoresist fully-reserved region, a thickness of the photoresist at the partially-exposed region is reduced so as to form a photoresist partially-reserved region, and the photoresist at the fully-exposed region is fully removed so as to form a photoresist fully-removed region;
a step of fully etching off the pixel electrode film corresponding to the photoresist fully-removed region by a first etching step;
a step of partially removing the barrier layer film corresponding to the photoresist fully-removed region by a second etching step;
a step of ashing and removing the photoresist according to a thickness of the photoresist partially-reserved region, so as to fully remove the photoresist at the photoresist partially-reserved region and reduce the thickness of the photoresist at the photoresist fully-reserved region;
a step of fully etching off the pixel electrode film corresponding to the photoresist partially-reserved region by a third etching step;
a step of fully etching off the remaining barrier layer film at the photoresist fully-removed region by a fourth etching step so as to expose the pattern of the active layer, thereby to form the pattern of the barrier layer having the pattern of the first via-hole and the pattern of the second via-hole connecting the pattern of the active layer and the source electrode and the drain electrode of the thin film transistor, the thickness of the barrier layer film remained in the photoresist fully-removed region being reduced due to the barrier layer film at the photoresist partially-reserved region; and
a step of removing the remaining photoresist so as to expose the pattern of the pixel electrode.

3. The method according to claim 1 , wherein prior to the first step, the method further comprises:
a step of forming a pattern of a gate line, a pattern of a gate electrode, and a pattern of a common electrode line on the base substrate by a patterning process.

4. The method according to claim 3 , wherein the fourth step further comprises:
a step of forming a data line and a channel region of the thin film transistor on the base substrate with the pattern of the barrier layer and the pattern of the pixel electrode;
a step of forming a passivation layer provided with a third via-hole on the base substrate with the data line, the source electrode, the drain electrode, and the channel region, so that the third via-hole is located in the second thickness region of the pattern of the barrier layer and penetrates through the passivation layer, the pattern of the barrier layer, and the pattern of the gate insulating layer to expose the common electrode line; and
a step of forming a pattern of a second electrode on the passivation layer so that the pattern of the second electrode is electrically connected to the common electrode line via the third via-hole.

5. The method according to claim 1 , wherein the photoresist is developed using a half-tone or gray-tone mask plate.

6. A display substrate, comprising:
a pattern of a gate insulating layer on a base substrate,
a pattern of an active layer on the pattern of the gate insulating layer,
a pattern of a barrier layer,
a pattern of a pixel electrode,
a pattern of a source electrode of a thin film transistor, and
a pattern of a drain electrode of the thin film transistor,
wherein,
the pattern of the barrier layer is located above the pattern of the gate insulating layer and the pattern of the active layer, and comprises a first via-hole region, a second via-hole region, a first thickness region, and a second thickness region;
the first via-hole region of the pattern of the barrier layer comprises a pattern of a first via-hole that penetrates the pattern of the barrier layer so as to expose a first part of the pattern of the active layer, and the pattern of the source electrode is connected to the first part of the pattern of the active layer through the first via-hole;
the second via-hole region of the pattern of the barrier layer comprises a pattern of a second via-hole that penetrates the pattern of the barrier layer so as to expose a second part of the pattern of the active layer, and the pattern of the drain electrode is connected to the second part of the pattern of the active layer through the second via

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Duan Xianxue
• Bai Mingji
• Xu Dezhi
• Zou Zhixiang

Classifications

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F2201/123

  pixel · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F2201/121

  common or background · CPC title