Superconductor analog to digital converter

Patent metadata

Field	Value
Publication number	US-10659075-B2
Application number	US-201916297571-A
Country	US
Kind code	B2
Filing date	Mar 8, 2019
Priority date	Aug 15, 2008
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

First claim

What is claimed is:

1. An analog to digital converter system, comprising:
an input configured to receive a signal;
a converter, configured to produce a stream of magnetic flux quanta, representing the signal as a set of parallel pulses, with an associated quantization error;
the converter being further configured to produce a residue signal representing the associated quantization error, amplified by a fluxon amplifier comprising an integral low pass filter;
a digitizer, configured to receive the residue signal representing the associated quantization error, and to produce therefrom a stream of quantized information, representing associated quantization error.

2. The analog to digital converter system according to claim 1 , further comprising a combiner, configured to combine the first stream of magnetic flux quanta with the second stream of quantized information to produce a composite stream representing the signal.

3. The analog to digital converter system according to claim 2 , wherein the first stream of magnetic flux quanta has a quantization noise, and the composite signal has a lower quantization noise than the first stream of magnetic flux quanta.

4. The analog to digital converter system according to claim 1 , wherein the first stream of magnetic flux quanta is delayed with respect to the signal stream, further comprising a compensating delay configured to time-synchronize the first stream of magnetic flux quanta and the signal, wherein the fluxon amplifier receives the time-synchronized first stream of magnetic flux quanta signal.

5. The analog to digital converter system according to claim 4 , wherein the compensating delay is digitally controllable.

6. The analog to digital converter system according to claim 1 , wherein the fluxon amplifier is configured to perform an integration, a filtering with the integral low pass filter, and a magnetic flux subtraction.

7. The analog to digital converter system according to claim 1 , wherein the converter produces a stream of magnetic flux quanta pulses having an average pulse timing, wherein respective pulses of the stream of magnetic flux quanta pulses are time modulated with respect to the average pulse timing.

8. A distributed fluxon amplifier, comprising:
a first coil configured to receive an analog signal;
a set of second coils configured to receive a set of quantized signals together representing the analog signal, comprising a quantization error with respect to the analog signal, the set of quantized signals being injected into the set of second coils as a plurality of independently generated pulses; and
a third coil configured to output a signal representing a difference between the analog signal and the set of quantized signals.

9. The distributed fluxon amplifier according to claim 8 , wherein the set of second coils have a range of time delays, wherein the set of second coils together low pass filter the set of quantized signals.

10. The distributed fluxon amplifier according to claim 9 , wherein the set of second coils have an incrementally increasing set of time delays.

11. The distributed fluxon amplifier according to claim 10 , wherein the incrementally increasing set of time delays are established in dependence on a clock signal.

12. The distributed fluxon amplifier according to claim 9 , wherein the range of time delays is controlled by a set of bias voltages.

13. The distributed fluxon amplifier according to claim 8 , wherein the set of quantized signals are generated by superconducting Josephson junction devices.

14. The distributed fluxon amplifier according to claim 8 , further comprising an analog-to-digital converter configured to digitize the signal representing a difference between the analog signal and the set of quantized signals.

15. The distributed fluxon amplifier according to claim 8 , wherein the second set of coils are driven by a parallel and series connected set of single flux quanta devices.

16. A distributed fluxon amplifier, comprising a series of coils receiving a set of single flux quanta (SFQ) signals through respective splitters, the respective coils of the series of coils being energized by the SFQ signals with a range of time delays controlled by a digital clock.

17. The distributed fluxon amplifier according to claim 16 , wherein the range of time delays is further controlled by a set of SFQ devices controlled with a range of bias voltages.

18. The distributed fluxon amplifier according to claim 16 , wherein at least one coil receives a signal from a plurality of SFQ devices in parallel, to amplify a power in the at least one coil over a power of a single SFQ device.

19. The distributed fluxon amplifier according to claim 16 , wherein a plurality of respective coils of the series of coils each receive a respective SFQ signal having an equal weighting.

20. The distributed fluxon amplifier according to claim 16 , wherein a plurality of respective coils of the series of coils each receive a respective SFQ signal having a binary-scaled weighting.

Assignees

• Hypres Inc

Inventors

• Inamdar Amol
• Gupta Deepnarayan

Classifications

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M3/02

  Delta modulation, i.e. one-bit differential modulation {(H03M3/30 takes precedence)} · CPC title

• H03M1/0854

  of quantisation noise · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title