PLL circuit

Patent metadata

Field	Value
Publication number	US-10659062-B2
Application number	US-201616342825-A
Country	US
Kind code	B2
Filing date	Dec 15, 2016
Priority date	Dec 15, 2016
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A lock detector ( 8 ) detects an unlocked state from an output of a phase frequency comparator ( 1 ). A counter ( 9 ) counts a reference signal, in a case where an unlocked state is detected by the lock detector ( 8 ). A parameter controlling circuit ( 10 ) acquires the count value of the counter ( 9 ), and controls switching on and off of a switch ( 12 ) for a D/A converter ( 11 ) that generates a signal to be added to an output of a loop filter ( 3 ), and the output voltage of the D/A converter ( 11 ) so that the count value of the counter ( 9 ) falls within a set value.

First claim

The invention claimed is:

1. A PLL circuit comprising:
a voltage-controlled oscillator to transmit a frequency signal corresponding to a voltage of a supplied signal;
a frequency divider to perform frequency dividing on an output of the voltage-controlled oscillator;
a phase frequency comparator to compare an output of the frequency divider with a reference signal;
a first charge pump to output a signal corresponding to a result of the comparison performed by the phase frequency comparator;
a loop filter to supply a signal obtained by smoothing the output signal of the first charge pump to the voltage-controlled oscillator;
a lock detector to detect a locked state and an unlocked state from an output of the phase frequency comparator;
a counter to be reset when an output of the lock detector switches from the locked state to the unlocked state, and to count the reference signal while the unlocked state is being detected;
a D/A converter to generate a signal to be added to an output of the loop filter;
a switch to switch whether to supply an output signal of the D/A converter; and
a parameter controlling circuit to acquire a count value of the counter, and control switching on and off of the switch and an output voltage of the D/A converter so that the count value of the counter is restricted within a set value.

2. The PLL circuit according to claim 1 , wherein the parameter controlling circuit performs the control at a time when a change in an output frequency of the PLL circuit is equal to or greater than a threshold value.

3. The PLL circuit according to claim 1 , wherein
a second charge pump for generating a signal to be added to an output of the first charge pump depending on a supplied parameter, is provided in place of the D/A converter and the switch of claim 1 , and
a parameter controlling circuit for acquiring a count value of the counter and controlling the parameter for the second charge pump to restrict the count value of the counter within a set value, is provided in place of the parameter controlling circuit of claim 1 .

Assignees

• Mitsubishi Electric Corp

Inventors

• Yanagihara Yuki
• Tsutsumi Koji
• Shimozawa Mitsuhiro

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03L7/095 Primary

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/101

  using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop (H03L7/113, H03L7/187 take precedence) · CPC title