Multi-phase clock generation circuit

Patent metadata

Field	Value
Publication number	US-10659059-B2
Application number	US-201916454982-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Oct 2, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A multi-phase clock circuit includes a first delay circuit, a second delay circuit, a third delay circuit, a first clock mixer circuit, and a second clock mixer circuit. The first, second, and third delay circuits are coupled in series. The first clock mixer circuit includes a first input and a second input. The first input is coupled to an output of the first delay circuit. The second input is coupled to an output of the second delay circuit. The second clock mixer circuit also includes a first input and a second input. The first input of the second clock mixer circuit is coupled to an output of the second delay circuit. The second input of the second clock mixer circuit is coupled to an output of the third delay circuit.

First claim

What is claimed is:

1. A multi-phase clock generation circuit, comprising:
a first delay circuit including first and second delay outputs, a second delay circuit including third and fourth delay outputs, and a third delay circuit including a fifth delay output, in which the first, second and third delay circuits are coupled in series;
a first clock mixer circuit including:
a first differential amplifier including first and second input terminals and first and second output terminals, the first input terminal coupled to the first delay output, and the second input terminal coupled to the second delay output; and
a second differential amplifier including third and fourth input terminals and third and fourth output terminals, the third input terminal coupled to the third delay output, the fourth input terminal coupled to the fourth delay output, the third output terminal coupled to the first output terminal, and the fourth output terminal coupled to the second output terminal; and

a second clock mixer circuit including fifth and sixth input terminals, the fifth input terminal coupled to the third delay output or to the fourth delay output, and the sixth input terminal coupled to the fifth delay output.

2. The multi-phase clock generation circuit of claim 1 , wherein:
the first delay circuit is configured to generate, at the first and second delay outputs, a first phase of a clock signal;
the second delay circuit is configured to generate, at the third and fourth delay outputs, a second phase of the clock signal; and
the third delay circuit is configured to generate, at the fifth delay output, a third phase of the clock signal.

3. The multi-phase clock generation circuit of claim 1 , wherein:
the first delay circuit includes a first circuit input adapted to be coupled to a clock;
the second delay circuit includes second and third circuit inputs, in which the second circuit input is coupled to the first delay output, and the third circuit input is coupled to the second delay output; and
the third delay circuit includes fourth and fifth circuit inputs, in which the fourth circuit input is coupled to the third delay output, and the fifth circuit input is coupled to the fourth delay outputs.

4. The multi-phase clock generation circuit of claim 1 , wherein the first clock mixer circuit is configured to average a first output signal from the first delay circuit and a second output signal from the second delay circuit.

5. The multi-phase clock generation circuit of claim 1 , wherein the first clock mixer circuit includes a current source coupled to the first differential amplifier and to the second differential amplifier.

6. The multi-phase clock generation circuit of claim 5 , wherein:
the first differential amplifier includes:
a first transistor including:
a gate terminal coupled to the first delay output;
a source terminal coupled to the current source; and
a drain terminal coupled to a first resistor; and

a second transistor including:
a gate terminal coupled to the second delay output;
a source terminal coupled to the current source; and
a drain terminal coupled to a second resistor; and

the second differential amplifier includes:
a third transistor including:
a gate terminal coupled to the third delay output;
a source terminal coupled to the current source; and
a drain terminal coupled to the drain terminal of the first transistor and to a third resistor; and

a fourth transistor including:
a gate terminal coupled to the fourth delay output;
a source terminal coupled to the current source; and
a drain terminal coupled to the drain terminal of the second transistor and to a fourth resistor.

7. A multi-phase clock generation circuit, comprising:
a delay-locked loop including:
a first delay circuit including a first circuit input and a first circuit output, the first circuit input adapted to be coupled to a clock, and the first delay circuit configured to provide a first delayed clock signal at the first circuit output responsive to a clock signal from the clock;
a second delay circuit including a second circuit input and a second circuit output, the second circuit input coupled to the first circuit output, and the second delay circuit configured to provide a second delayed clock signal at the second circuit output responsive to the first delayed clock signal; and
a third delay circuit including a third circuit input and a third circuit output, the third circuit input coupled to the second circuit output, and the third delay circuit configured to provide a third delayed clock signal at the third circuit output responsive to the second delayed clock signal;

a first clock mixer circuit including first and second mixer inputs, the first mixer input coupled to the first circuit output, the second mixer input coupled to the second circuit output, the first clock mixer circuit configured to combine the first and second delayed clock signals, and the first clock mixer circuit including:
a first differential amplifier configured to amplify the first delayed clock signal; and
a second differential amplifier coupled to the first differential amplifier and configured to amplify the second delayed clock signal; and

a second clock mixer circuit including third and fourth mixer inputs, the third mixer input coupled to the second circuit output, the fourth mixer input coupled to the third circuit output, and the second clock mixer circuit configured to combine the second and third delayed clock signals.

8. The multi-phase clock generation circuit of claim 7 , wherein:
the first delay circuit is configured to change a phase of the clock signal by 45 degrees;
the second delay circuit is configured to change a phase of the first delayed clock signal by 45 degrees; and
the third delay circuit is configured to change a phase of the second delayed clock signal by 45 degrees.

9. The multi-phase clock generation circuit of claim 7 , wherein:
the first clock mixer circuit includes a first mixer output, and the first clock mixer circuit is configured to provide a first output clock signal at the first mixer output, the first output clock signal having a phase that is an average of a phase of the first delayed clock signal and a phase of the second delayed clock signal; and
the second clock mixer circuit includes a second mixer output, and the second clock mixer circuit is configured to provide a second output clock signal at the second mixer output, the second output clock signal having a phase that is an average of the phase of the second delayed clock signal and a phase of the third delayed clock signal.

10. The multi-phase clock generation circuit of claim 7 , wherein the first clock mixer circuit includes a current source coupled to the first differential amplifier and to the second differential amplifier.

11. The multi-phase clock generation circuit of claim 7 , wherein:
the first circuit output includes first and second differential outputs;
the second circuit output includes third and fourth differential outputs;
the first differential amplifier includes:
a first input terminal coupled to the first differential output;
a second input terminal coupled to the second differential output;
a first output terminal; and
a second output terminal; and

the second differential amplifier includes:
a third input terminal coupled to the third differential output;
a fourth input terminal coupled to the fourth differential output;
a third output terminal coupled to the first output terminal; and
a fourth output terminal coupled to the second output terminal.

12. The multi-phase clock generation circuit of claim 11 , wherein:

Assignees

• Texas Instruments Inc

Inventors

• Payne Robert Floyd
• Pope Olga Pavlovna

Classifications

• H03F2203/45026

  One or more current sources are added to the amplifying transistors in the differential amplifier · CPC title

• H03L7/0818 Primary

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45374

  the AAC comprising one or more discrete resistors · CPC title

• H03D7/125

  with field effect transistors · CPC title