Memory cell switch device

Patent metadata

Field	Value
Publication number	US-10658588-B2
Application number	US-201715480782-A
Country	US
Kind code	B2
Filing date	Apr 6, 2017
Priority date	Apr 6, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Memory structures with a plurality of memory cells that each include memory devices in combination with switch devices are provided. The memory device and switch device of each cell are connected in series, and include at least first and second electrodes. The first electrode features a relatively high resistance, to provide a reduced snap current during operation of the memory device. The first electrode with a relatively high resistance can contain or be entirely composed of TiAlN.

First claim

What is claimed is:

1. A method for producing a first electrode of a memory cell, comprising:
depositing a layer of TiN on a substrate;
depositing a layer of AlN on the substrate;
repeating the steps of depositing a layer of TiN and of depositing a layer of AlN multiple times; and
after repeating the steps of depositing a layer of TiN and of depositing a layer of AlN multiple times, performing NH 3 annealing of the deposited layers,
wherein the first electrode includes titanium aluminum nitride (TiAlN).

2. The method of claim 1 , wherein the first electrode is formed entirely from TiAlN.

3. The method of claim 1 , wherein the first electrode is at least 70% Al.

4. The method of claim 1 , wherein a resistance of the first electrode is at least 12,500 Ohms.

5. The method of claim 1 , wherein the steps of depositing a layer of TiN and of depositing a layer of AlN is repeated 135 times.

6. The method of claim 1 , wherein depositing the layer of TiN comprises using a nitrogen carrier flow into which titanium tetrachloride (TiCl 4 ) is introduced.

7. The method of claim 1 , wherein depositing the layer of AlN comprises using a nitrogen carrier flow into which trimethylaluminum (TMA) is introduced.

8. The method of claim 1 , wherein the first electrode has a thickness of 400 A.

9. The method of claim 1 , wherein the first electrode is formed using atomic layer deposition (ALD).

10. The method of claim 1 , wherein the first electrode features reduced current at elevated voltages.

11. The method of claim 1 , wherein the first electrode provides an increased electrical resistance with a reduced peak current.

12. The method of claim 1 , wherein the layer of AlN is deposited on the substrate first.

Assignees

• Yasuda Shuichiro
• Tsushima Tomohito
• Sony Corp

Inventors

• Yasuda Shuichiro
• Tsushima Tomohito

Classifications

• G11C2213/52

  Structure characterized by the electrode material, shape, etc. · CPC title

• G11C2213/11

  Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites · CPC title

• G11C13/003

  Cell access · CPC title

• G11C2213/56

  Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title