High-speed superjunction lateral insulated gate bipolar transistor

Patent metadata

Field	Value
Publication number	US-10658496-B2
Application number	US-201916264654-A
Country	US
Kind code	B2
Filing date	Jan 31, 2019
Priority date	Feb 10, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

The present disclosure relates to a high-speed superjunction lateral insulated gate bipolar transistor, and belongs to the technical field of semiconductor power devices. Fast turn-off can be achieved by replacing the lightly doped substrate of the existing bulk silicon superjunction lateral insulated gate bipolar transistor with heavily doped substrate, breakdown voltage of the device is ensured by reasonably setting the total number of impurities in each drift region of the over junction-sustaining voltage layer, and further application thereof in integrated circuits is realized by providing the semiconductor second substrate region and the semiconductor isolation region. A high speed superjunction laterally insulated gate bipolar transistor according to the present disclosure solves the contradiction between cost of the superjunction laterally insulated gate bipolar transistor and achievement of fast turn-off on a bulk silicon substrate.

First claim

What is claimed is:

1. A high-speed superjunction lateral insulated gate bipolar transistor, characterized in that a cell structure of the transistor comprises:
a semiconductor first substrate region;
a voltage-sustaining region, which is located on a surface of the semiconductor first substrate region, and comprises mutually alternating semiconductor first drift regions and semiconductor second drift regions of different conductivity types, the semiconductor first drift region has a conductivity type the same as that of the semiconductor first substrate region, and the semiconductor second drift region has a conductivity type opposite to that of the semiconductor first substrate region, the conductivity type being N type or P type;
a semiconductor field stop region having a conductivity type the same as that of the semiconductor first substrate region and located on a surface of the semiconductor first substrate region, wherein at least one semiconductor collector region having a conductivity type opposite to that of the semiconductor first substrate region is provided in the semiconductor field stop region, and a portion of a surface of the semiconductor collector region is covered with a conductor to form a collector of the transistor;
a semiconductor body region having a conductivity type opposite to that of the semiconductor first substrate region;
a semiconductor emitter region having a conductivity type the same as that of the semiconductor first substrate region and located in the semiconductor body region, a portion of the semiconductor body region and a portion of the semiconductor emitter region being connected by a conductor to form an emitter of the transistor;
a gate insulating layer covering a portion of a surface of the semiconductor emitter region, a portion of a surface of the semiconductor body region, and a portion of a surface of the voltage-sustaining region, wherein a semiconductor polysilicon gate region covering a surface of the gate insulating layer and a conductor covering the semiconductor polysilicon gate region form a gate electrode of the transistor, the gate region has a conductivity type the same as that of the semiconductor first substrate region; and a portion of the semiconductor emitter region, a portion of the semiconductor body region, the gate insulating layer, the semiconductor polysilicon gate region, the gate electrode and a portion of the voltage-sustaining region form a gate structure of the transistor;
wherein the semiconductor first drift region and the semiconductor second drift region are in contact with each other and contact surfaces are perpendicular to the semiconductor first substrate region and the semiconductor field stop region;
the voltage-sustaining region and the semiconductor field stop region are in contact with each other and a contact surface is perpendicular to the semiconductor first substrate region.

2. The high-speed superjunction lateral insulated gate bipolar transistor of claim 1 wherein:
the semiconductor field stop region is in contact with the semiconductor collector region through a semiconductor buffer region having a conductivity type the same as that of the semiconductor first substrate region, wherein the semiconductor buffer region is located in the semiconductor field stop region, and the semiconductor collector region is located in the semiconductor buffer region.

3. The high-speed superjunction lateral insulated gate bipolar transistor of claim 1 wherein:
the semiconductor field stop region is in contact with the semiconductor collector region through a semiconductor auxiliary region having a conductivity type opposite to that of the semiconductor first substrate region, wherein a contact surface is perpendicular to the semiconductor first substrate region, the semiconductor collector region is located in the semiconductor auxiliary region, and the semiconductor auxiliary region adopts an impurity concentration distribution the same as that of the semiconductor second drift region.

4. The high-speed superjunction lateral insulated gate bipolar transistor of claim 1 wherein:
the cell structure further comprises a second substrate region located on a bottom surface of the semiconductor first substrate region and having a doping concentration lower than that of the semiconductor first substrate region.

5. The high-speed superjunction lateral insulated gate bipolar transistor of claim 4 wherein:
the semiconductor field stop region is further in contact with the semiconductor collector region by a semiconductor buffer region having a conductivity type the same as the semiconductor first substrate region, wherein the semiconductor buffer region is located in the semiconductor field stop region, and the semiconductor collector region is located in the semiconductor buffer region.

6. The high-speed superjunction lateral insulated gate bipolar transistor of claim 4 wherein:
the semiconductor field stop region is further in contact with the semiconductor collector region through a semiconductor auxiliary region having a conductivity type opposite to that of the semiconductor first substrate region, wherein a contact surface is perpendicular to the semiconductor first substrate region, the semiconductor collector region is located in the semiconductor auxiliary region, and the semiconductor auxiliary region adopts an impurity concentration distribution the same as that of the semiconductor second drift region.

7. The high-speed superjunction lateral insulated gate bipolar transistor of claim 4 wherein:
the semiconductor field stop region is provided with at least one semiconductor first isolation region having a conductivity type the same as that of the semiconductor first substrate region, the semiconductor first isolation region and the semiconductor first substrate region are in contact with each other; a contact surface of the semiconductor field stop region and the semiconductor first isolation region is perpendicular to the semiconductor first substrate region.

8. The high-speed superjunction lateral insulated gate bipolar transistor of claim 7 wherein:
the semiconductor field stop region is further in contact with the semiconductor collector region through a semiconductor buffer region having a conductivity type the same as that of the semiconductor first substrate region, wherein the semiconductor buffer region is located in the semiconductor field stop region, and the semiconductor collector region is located in the semiconductor buffer region.

9. The high-speed superjunction lateral insulated gate bipolar transistor of claim 6 wherein:
the semiconductor auxiliary region is provided with at least one semiconductor second isolation region having a conductivity type the same as that of the semiconductor first substrate region, the semiconductor second isolation region and the semiconductor first substrate region are in contact with each other; a contact surface of the semiconductor auxiliary region and the semiconductor second isolation region is perpendicular to the semiconductor first substrate region.

10. The high-speed superjunction lateral insulated gate bipolar transistor of claim 1 wherein:
the semiconductor first substrate region is a heavily doped region having a doping concentration greater than 10 18 cm −3 .

Assignees

• Univ Chongqing

Inventors

• Lin Zhi
• Yuan Qi
• Han Shu
• Hu Shengdong
• Zhou Jianlin
• Tang Fang
• Zhou Xichuan

Classifications

• H01L29/0808

  Electricity · mapped topic

• H01L29/0834

  Electricity · mapped topic

• H01L29/0634

  Electricity · mapped topic

• H01L29/0821

  Electricity · mapped topic

• H01L29/7394

  Electricity · mapped topic