Three-dimensional semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10658375-B2
Application number	US-201815975861-A
Country	US
Kind code	B2
Filing date	May 10, 2018
Priority date	Jun 23, 2014
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

First claim

What is claimed is:

1. A method of fabricating a three-dimensional semiconductor memory device, comprising:
forming a peripheral circuit device and a peripheral interconnection structure on a substrate;
forming a lower mold insulating layer to cover the peripheral circuit device and the peripheral interconnection structure;
forming a horizontal active layer on the lower mold insulating layer, the horizontal active layer comprising first, second, and third active semiconductor layers sequentially stacked on the lower mold insulating layer;
forming a cell array structure on the horizontal active layer;
forming a pick-up region in the horizontal active layer and around the cell array structure, wherein the pick-up region is formed to have the first conductivity type; and
forming a pick-up diffusion barrier region in the third active semiconductor layer to surround at least a portion of a side surface of the pick-up region, wherein the pick-up diffusion barrier region comprises carbon,
wherein the first active semiconductor layer is doped with impurities to have a first conductivity type and a first concentration, the second active semiconductor layer comprises an impurity diffusion restraining material inhibiting diffusion of the impurities in the first active semiconductor layer into the second active semiconductor layer, and the third active semiconductor layer is doped with impurities to have the first conductivity type and a second concentration different from the first concentration, or is in an undoped state.

2. The method of claim 1 , wherein the forming of the cell array structure comprises:
forming a plurality of stacks arranged parallel to each other,
forming vertical structures penetrating the stacks, and
forming a common source region between ones of the stacks to extend parallel to the stacks.

3. The method of claim 1 , wherein the second active semiconductor layer comprises carbon.

4. The method of claim 1 , wherein the forming of the peripheral circuit device and the peripheral interconnection structure comprises:
forming the peripheral circuit device on the substrate, the peripheral circuit device comprising a gate electrode and source/drain regions, and
forming the peripheral interconnection structure on the substrate, the peripheral interconnection structure comprising a contact connected to the peripheral circuit device and an interconnection line connected to the contact.

5. The method of claim 1 , further comprising forming a contact connected to the pick-up region.

6. The method of claim 1 , further comprising sequentially forming a buffer insulating layer and a fourth active semiconductor layer on the third active semiconductor layer.

7. The method of claim 6 , further comprising terming a semiconductor pattern penetrating the buffer insulating layer and the fourth active semiconductor layer and being in contact with the third active semiconductor layer.

8. The method of claim 6 , wherein the cell array structure comprises a plurality of stacks arranged parallel to each other, vertical structures penetrating the stacks, and a common source region between the stacks to extend parallel to the stacks, and
wherein the forming of the common source region comprises forming an impurity region in the fourth active semiconductor layer to have a second conductivity type.

9. A method of fabricating a three-dimensional semiconductor memory device, comprising:
forming a peripheral circuit device and a peripheral interconnection structure on a substrate;
forming a lower mold insulating layer to cover the peripheral circuit device and the peripheral interconnection structure;
forming a horizontal active layer on the lower mold insulating layer, the horizontal active layer comprising first, second, and third active semiconductor layers sequentially stacked on the lower mold insulating layer; and
forming a cell array structure on the horizontal active layer,
wherein the first active semiconductor layer is doped with impurities to have a first conductivity type and a first concentration, the second active semiconductor layer comprises an impurity diffusion restraining material inhibiting diffusion of the impurities in the first active semiconductor layer into the second active semiconductor layer, and the third active semiconductor layer is doped with impurities to have the first conductivity type and a second concentration different from the first concentration, or is in an undoped state,
wherein a cell array comprises a plurality of stacks provided parallel to a first direction on the horizontal active layer, each of the stacks comprising a plurality of electrodes vertically stacked on the horizontal active layer, such that a topmost one of the first, second, and third active semiconductor layers of the horizontal active layer is between the substrate and lowermost electrodes of the plurality of electrodes.

10. The method of claim 9 , wherein the forming of the horizontal active layer comprises:
forming the second active semiconductor layer, which is doped with carbon, directly on the first active semiconductor layer, and
forming the third active semiconductor layer directly on the second active semiconductor layer.

11. The method of claim 10 , further comprising sequentially thrilling a buffer insulating layer and a fourth active semiconductor layer on the third active semiconductor layer.

12. The method of claim 9 , further comprising forming a pick-up region in the horizontal active layer, wherein the pick-up region is connected to a first contact and is formed to have the first conductivity type.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yon Gukhyon
• Kim Dongwoo
• Hwang Kihyun
• Kim Dongkyum
• Yoo Dongchul

Classifications

• H01L27/249

  Electricity · mapped topic

• H01L27/2436

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic

• H01L45/1226

  Electricity · mapped topic