Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof

Patent metadata

Field	Value
Publication number	US-10658364-B2
Application number	US-201815908575-A
Country	US
Kind code	B2
Filing date	Feb 28, 2018
Priority date	Feb 28, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

First claim

The invention claimed is:

1. A method of making a ROM cell comprising:
forming an EEPROM cell having a floating gate, a control gate, a first well and a selection gate;
forming a metal line overlying the EEPROM cell; and
converting the EEPROM cell to ROM cell by forming a contact between the metal line and the floating gate, wherein the contact connects the floating gate to the selection gate.

2. A method of making a ROM cell comprising:
forming an EEPROM cell having a floating gate, a control gate, a first well and a selection gate;
forming a metal line overlying the EEPROM cell; and
converting the EEPROM cell to ROM cell by forming a contact between the metal line and the floating gate, wherein the contact connects the floating gate to the first well.

3. The method of claim 1 , including forming a first set of EEPROM cells and a second set of EEPROM cells, wherein forming the first set includes forming the EEPROM cell.

4. The method of claim 3 further including:
converting the first set of EEPROM cells into ROM cells; and
maintaining the second set of EEPROM cells as EEPROM cells.

5. The method of claim 1 further including forming a second well at the same time the first well is formed.

6. The method of claim 5 wherein the control gate is in the second well.

7. A method of forming a memory comprising:
forming an EEPROM cell, the EEPROM cell having a well, a floating gate overlying the well, a control gate and a selection gate; and
converting the EEPROM cell into a ROM cell, wherein the converting comprises:
electrically connecting the floating gate to the selection gate.

8. A method of forming a memory comprising:
forming an EEPROM cell, the EEPROM cell having a well, a floating gate overlying the well, a control gate and a selection gate; and
converting the EEPROM cell into a ROM cell, wherein the converting step comprises:
electrically connecting the floating gate to the well.

9. The method of claim 7 further including:
forming a metal line overlying the EEPROM cell.

10. The method of claim 9 , comprising forming a polysilicon line, wherein the converting step includes
forming a contact between the metal line and the polysilicon line.

11. The method of claim 8 , further including:
forming a metal line overlying the EEPROM cell.

12. The method of claim 11 , comprising forming a polysilicon line, wherein the converting step includes forming a contact between the metal line and the polysilicon line.

13. The method of claim 2 , including forming a first set of EEPROM cells and a second set of EEPROM cells, wherein forming the first set includes forming the EEPROM cell.

14. The method of claim 13 , further including:
converting the first set of EEPROM cells into ROM cells; and
maintaining the second set of EEPROM cells as EEPROM cells.

15. The method of claim 2 , further including forming a second well at the same time the first well is formed.

16. The method of claim 15 , wherein the control gate is in the second well.

17. A method of making a ROM cell, comprising:
forming an EEPROM cell having a floating gate, a control gate, a first well and a selection gate;
forming a metal line overlying the EEPROM cell;
converting the EEPROM cell to ROM cell by forming a contact between the metal line and the floating gate; and
forming a second well at the same time the first well is formed, wherein the control gate is in the second well.

18. The method of claim 1 , including forming a first set of EEPROM cells and a second set of EEPROM cells, wherein forming the first set includes forming the EEPROM cell.

19. The method of claim 18 , further including:
converting the first set of EEPROM cells into ROM cells; and
maintaining the second set of EEPROM cells as EEPROM cells.

Assignees

• St Microelectronics Int Nv
• St Microelectronics Srl

Inventors

• De Santis Fabio
• Rana Vikas

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C29/82

  for EEPROMs · CPC title

• G11C17/12

  using field-effect devices · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C2216/10

  Floating gate memory cells with a single polysilicon layer · CPC title