Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process

Patent metadata

Field	Value
Publication number	US-10658361-B2
Application number	US-201113997624-A
Country	US
Kind code	B2
Filing date	Dec 28, 2011
Priority date	Dec 28, 2011
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

First claim

What is claimed is:

1. A device comprising:
a substrate having a plurality of semiconductor fins;
a first transistor having a first gate structure that wraps around a first semiconductor fin, wherein the first gate structure comprises a first gate dielectric structure in direct contact with the first semiconductor fin and a first gate electrode structure comprising a first metal layer, the first metal layer in direct contact with the first gate dielectric structure, wherein the first gate dielectric structure comprises a first gate dielectric layer and a second gate dielectric layer on the first gate dielectric layer, the first transistor having a first pair of n type doped source/drain regions on opposite sides of the first gate structure; and
a second transistor isolated from the first transistor, the second transistor having a second gate structure that wraps around a second semiconductor fin wherein the second gate structure comprises a second gate dielectric structure in direct contact with the second semiconductor fin and a second gate electrode structure comprising a second metal layer, the second metal layer in direct contact with the second gate dielectric structure, the second transistor having a second pair of n type doped source/drain regions on opposite sides of the second gate structure, wherein the second gate dielectric structure comprises the second gate dielectric layer but not the first gate dielectric layer, wherein the second gate dielectric structure is different in composition from the first gate dielectric structure, and wherein the second gate electrode structure is different in composition than the first gate electrode structure.

2. The device of claim 1 wherein the first gate dielectric layer comprises silicon dioxide and wherein the second gate dielectric layer is a first high k dielectric layer.

3. The device of claim 1 wherein the first semiconductor fin comprises the same semiconductor material as the second semiconductor fin.

4. A device comprising:
a substrate having a plurality of semiconductor fins, the semiconductor fins comprising a semiconductor material;
a first transistor having a first gate structure that wraps around one or more of the semiconductor fins, wherein the first gate structure comprises a first gate dielectric structure in direct contact with the semiconductor material of a top surface of the one or more semiconductor fins that the first gate structure wraps around and a first gate electrode structure comprising a first work function metal layer, the first work function metal layer in direct contact with the first gate dielectric structure, the first transistor having a first pair of n type doped source/drain regions on opposite sides of the first gate structure, wherein the first gate dielectric structure comprises a first high k dielectric layer and wherein the first gate electrode structure comprises the first work function metal layer and a fill metal; and
a second transistor isolated from the first transistor, the second transistor having a second gate structure that wraps around one or more of the semiconductor fins, wherein the second gate structure comprises a second gate dielectric structure in direct contact with the semiconductor material of a top surface of the one or more semiconductor fins which the second gate structure wraps around and a second gate electrode structure comprising a second work function metal layer, the second work function metal layer in direct contact with the second gate dielectric structure, the second transistor having a second pair of n type doped source/drain regions on opposite sides of the second gate structure, wherein the second gate dielectric structure is different in composition from the first gate dielectric structure along the top surface and sidewalls of the corresponding one or more of the semiconductor fins, and wherein the second gate electrode structure is different in composition than the first gate electrode structure, wherein the second gate electrode structure comprises the first work function metal layer and the second work function metal layer, wherein the second work function metal layer is different in composition than the first work function metal layer.

5. A device comprising:
a substrate having a plurality of semiconductor fins, the semiconductor fins comprising a semiconductor material;
a first transistor having a first gate structure that wraps around one or more of the semiconductor fins, wherein the first gate structure comprises a first gate dielectric structure in direct contact with the semiconductor material of a top surface of the one or more semiconductor fins that the first gate structure wraps around and a first gate electrode structure comprising a first work function metal layer, the first work function metal layer in direct contact with the first gate dielectric structure, the first transistor having a first pair of n type doped source/drain regions on opposite sides of the first gate structure, wherein the first gate dielectric structure comprises a first high k dielectric layer and wherein the first gate electrode structure comprises the first work function metal layer and a fill metal;
a second transistor isolated from the first transistor, the second transistor having a second gate structure that wraps around one or more of the semiconductor fins, wherein the second gate structure comprises a second gate dielectric structure in direct contact with the semiconductor material of a top surface of the one or more semiconductor fins which the second gate structure wraps around and a second gate electrode structure comprising a second work function metal layer, the second work function metal layer in direct contact with the second gate dielectric structure, the second transistor having a second pair of n type doped source/drain regions on opposite sides of the second gate structure, wherein the second gate dielectric structure is different in composition from the first gate dielectric structure along the top surface and sidewalls of the corresponding one or more of the semiconductor fins, and wherein the second gate electrode structure is different in composition than the first gate electrode structure; and
a third transistor, wherein the third transistor has a third gate structure comprising a third gate dielectric structure and the first gate electrode structure wherein the third gate dielectric structure is different in composition than the first gate dielectric structure.

6. The device of claim 5 , further comprising a fourth transistor, wherein the fourth transistor has a fourth gate structure comprising a fourth gate dielectric structure and the first gate electrode structure, wherein the fourth gate dielectric structure comprises a silicon dioxide layer, the first high k dielectric layer, and a second high k dielectric layer.

7. A device comprising:
a substrate having a plurality of semiconductor fins, the semiconductor fins comprising a semiconductor material;
a first transistor having a first gate structure that wraps around one or more of the semiconductor fins, wherein the first gate structure comprises a first gate dielectric structure in direct contact with the semiconductor material of a top surface of the one or more semiconductor fins that the first gate structure wraps around and a first gate electrode structure comprising a first work function metal layer, the first work function metal layer in direct contact with the first gate dielectric structure, the first transistor having a first pair of n type doped source/drain regions on opposite sides of the first gate structure, wherein the first gate dielectric structure comprises a first high k dielectric layer and wherein the first gate electrode structure comprises the first work function meta

Assignees

• Tsai Curtis
• Jan Chia Hong
• Yeh Jeng Ya David
• Park Joodong
• Hafez Walid M
• Intel Corp

Inventors

• Tsai Curtis
• Jan Chia-Hong
• Yeh Jeng-Ya David
• Park Joodong
• Hafez Walid M

Classifications

• H01L29/42364

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic

• H01L27/0922 Primary

  Electricity · mapped topic

• H01L29/401

  Electricity · mapped topic

• H01L29/517

  Electricity · mapped topic